59 input mclk,
// global clock, half DDR3 clock, synchronizes all I/O through the command port 60 // programming interface 61 input [
7:
0]
cmd_ad,
// byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 62 input cmd_stb,
// strobe (with first byte) for the command a/d 63 output [
7:
0]
status_ad,
// status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25] 64 output status_rq,
// input request to send status downstream 65 input status_start,
// Acknowledge of the first status packet byte (address) 96 localparam PAGE_BITS=
4;
// number of LSB to indicate pages read/written 264 )
cmd_deser_mcontr_test01_8bit_i (
265 .
rst (
1'b0),
// rst), // input 277 .
rst (
1'b0),
// rst), // input 301 )
status_generate_chn1_i (
302 .
rst (
1'b0),
// rst), // input 316 )
status_generate_chn2_i (
317 .
rst (
1'b0),
// rst), // input 331 )
status_generate_chn3_i (
332 .
rst (
1'b0),
// rst), // input 346 )
status_generate_chn4_i (
347 .
rst (
1'b0),
// rst), // input
5127frame_start_chn4_rreg
5120page_chn1reg[PAGE_BITS-1:0]
5125frame_start_chn2_rreg
5100STATUS_PAYLOAD_BITSFRAME_HEIGHT_BITS+PAGE_BITS+2
5105status_chn1_adwire[7:0]
5060MCNTRL_TEST01_CHN3_MODE'h6
5062MCNTRL_TEST01_CHN4_MODE'h8
5152frame_finished_chn2reg
[FRAME_HEIGHT_BITS-1:0] 5079line_unfinished_chn1
5144cmd_frame_start_wwire
5154frame_finished_chn4reg
5111status_chn2_startwire
5126frame_start_chn3_rreg
5056MCNTRL_TEST01_CHN1_MODE'h2
5124frame_start_chn1_rreg
5115status_chn3_startwire
5151frame_finished_chn1reg
5109status_chn2_adwire[7:0]
[ADDR_MASK2!=0?2:ADDR_MASK1!=0?1:0:0] 9935we
5061MCNTRL_TEST01_CHN3_STATUS_CNTRL'h7
status_router4_i status_router4
5064MCNTRL_TEST01_STATUS_REG_CHN1_ADDR'h3c
5153frame_finished_chn3reg
5112status_chn3wire[STATUS_PAYLOAD_BITS-1:0]
5108status_chn2wire[STATUS_PAYLOAD_BITS-1:0]
5116status_chn4wire[STATUS_PAYLOAD_BITS-1:0]
[FRAME_HEIGHT_BITS-1:0] 5097line_unfinished_chn4
5122page_chn3reg[PAGE_BITS-1:0]
[DATA_WIDTH-1:0] 9934data
5119status_chn4_startwire
5053MCNTRL_TEST01_ADDR'h0f0
status_generate_chn4_i status_generate
5065MCNTRL_TEST01_STATUS_REG_CHN2_ADDR'h3d
5121page_chn2reg[PAGE_BITS-1:0]
5066MCNTRL_TEST01_STATUS_REG_CHN3_ADDR'h3e
5058MCNTRL_TEST01_CHN2_MODE'h4
[FRAME_HEIGHT_BITS-1:0] 5085line_unfinished_chn2
[ADDR_WIDTH-1:0] 9933addr
5113status_chn3_adwire[7:0]
5059MCNTRL_TEST01_CHN2_STATUS_CNTRL'h5
5104status_chn1wire[STATUS_PAYLOAD_BITS-1:0]
[FRAME_HEIGHT_BITS-1:0] 5091line_unfinished_chn3
5117status_chn4_adwire[7:0]
cmd_deser_mcontr_test01_8bit_i cmd_deser
5063MCNTRL_TEST01_CHN4_STATUS_CNTRL'h9
[ALL_BITS-1:0] 10777status
5107status_chn1_startwire
5123page_chn4reg[PAGE_BITS-1:0]
5067MCNTRL_TEST01_STATUS_REG_CHN4_ADDR'h3f
5057MCNTRL_TEST01_CHN1_STATUS_CNTRL'h3
5054MCNTRL_TEST01_MASK'h7f0