level_cross_clocks.v

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`timescale 1ns/1ps

module  level_cross_clocks#(
    parameter WIDTH = 1,
    parameter REGISTER = 2, // number of registers (>=12)
    parameter FAST0 = 1'b0,
    parameter FAST1 = 1'b0
)(
    input              clk,
    input  [WIDTH-1:0] d_in,
    output [WIDTH-1:0] d_out
);
    generate
        genvar i;
        for (i = 0; i < WIDTH ; i = i+1) begin: level_cross_clock_block
            if (REGISTER <= 1)
                level_cross_clocks_ff_bit  #(.FAST1(FAST1))  level_cross_clocks_single_i ( // just a single ff (if metastability is not a problem)
                    .clk   (clk),       // input
                    .d_in  (d_in[i]),   // input
                    .d_out (d_out[i])   // output
                );
            else if (REGISTER == 2)
                level_cross_clocks_sync_bit  #(.FAST0(FAST0),.FAST1(FAST1))  level_cross_clocks_sync_i ( // classic 2-register synchronizer
                    .clk   (clk),       // input
                    .d_in  (d_in[i]),   // input
                    .d_out (d_out[i])   // output
                );
            else
                level_cross_clocks_single_bit #( // >2 bits (first two only are synchronizer)
                    .REGISTER(REGISTER), .FAST0(FAST0), .FAST1(FAST1)
                ) level_cross_clocks_single_i (
                    .clk   (clk),       // input
                    .d_in  (d_in[i]),   // input
                    .d_out (d_out[i])   // output
                );
        end
    endgenerate
endmodule

module  level_cross_clocks_single_bit#(
    parameter REGISTER = 3, // number of registers (>=3)
    parameter FAST0 = 1'b0,
    parameter FAST1 = 1'b0
)(
    input   clk,
    input   d_in,
    output  d_out
);
    reg  [REGISTER - 3 : 0] regs = {REGISTER -2 {FAST1}};
    wire                    d_sync; // after a 2-bit synchronizer
    wire [REGISTER - 2 : 0] regs_next = {regs, d_sync};
    assign d_out = regs[REGISTER -3];
    always @ (posedge clk) begin
        if      (FAST0)  regs <= {REGISTER - 3{d_in}} & regs_next[REGISTER - 3 : 0];   
        else if (FAST1)  regs <= {REGISTER - 3{d_in}} | regs_next[REGISTER - 3 : 0];   
        else             regs <=                        regs_next[REGISTER - 3 : 0]; // | d_in complains about widths mismatch
    end
    level_cross_clocks_sync_bit #(.FAST0(FAST0),.FAST1(FAST1)) level_cross_clocks_sync_bit_i (
        .clk   (clk), // input
        .d_in  (d_in), // input
        .d_out (d_sync) // output
    );
endmodule

// Classic 2-bit (exactly) synchronizer
module  level_cross_clocks_sync_bit #(
    parameter FAST0 = 1'b0,
    parameter FAST1 = 1'b0
)(
    input   clk,
    input   d_in,
    output  d_out
);
`ifndef IGNORE_ATTR
    (* ASYNC_REG = "TRUE" *)
`endif
    reg  [1:0] sync_zer; 
    assign d_out = sync_zer [1];
    always @ (posedge clk) begin
        if      (FAST0) sync_zer <= {sync_zer[0] & d_in, d_in};
        else if (FAST1) sync_zer <= {sync_zer[0] | d_in, d_in};
        else            sync_zer <= {sync_zer[0],d_in};
    end
endmodule

module  level_cross_clocks_ff_bit #( // just a single FF if REGISTER == 1 (if metastability is not a problem)
    parameter FAST1 = 1'b0
) (
    input       clk,
    input      d_in,
    output     d_out
);
    reg d_out_r = FAST1;
    assign d_out = d_out_r;
    always @ (posedge clk) begin
        d_out_r <= d_in;
    end
endmodule