Static Public Member Functions

Always Constructs
ALWAYS_375	( ipclk )
ALWAYS_376	( pclk or async_prst_with_sens_mrst )
ALWAYS_377	( mclk )
ALWAYS_378	( ipclk )
ALWAYS_379	( mclk )
ALWAYS_380	( mclk )

Public Attributes

Inputs
pclk
mclk_rst
prst
trigger_mode
trig
status_alive_1cyc	[STATUS_ALIVE_WIDTH - 1 : 0 ]
mclk
cmd_ad	[ 7 : 0 ]
cmd_stb
status_start

Inouts
vact
hact
bpf
pxd	[ 11 : 0 ]
mrst
senspgm
arst
aro

Outputs
prsts
irst
ipclk
ipclk2x
dclk
pxd_out	reg [ 11 : 0 ]
vact_out	reg
hact_out
status_ad	[ 7 : 0 ]
status_rq

Parameters
SENSIO_ADDR	'h330
SENSIO_ADDR_MASK	'h7f8
SENSIO_CTRL	'h0
SENSIO_STATUS	'h1
SENSIO_JTAG	'h2
SENSIO_WIDTH	'h3
SENSIO_DELAYS	'h4
SENSIO_STATUS_REG	'h21
SENS_JTAG_PGMEN	8
SENS_JTAG_PROG	6
SENS_JTAG_TCK	4
SENS_JTAG_TMS	2
SENS_JTAG_TDI	0
SENS_CTRL_MRST	0
SENS_CTRL_ARST	2
SENS_CTRL_ARO	4
SENS_CTRL_RST_MMCM	6
SENS_CTRL_EXT_CLK	8
SENS_CTRL_LD_DLY	10
SENS_CTRL_QUADRANTS	12
SENS_CTRL_QUADRANTS_WIDTH	6
SENS_CTRL_QUADRANTS_EN	20
LINE_WIDTH_BITS	16
IODELAY_GRP	"IODELAY_SENSOR"
IDELAY_VALUE	integer 0
PXD_DRIVE	integer 12
PXD_IBUF_LOW_PWR	"TRUE"
PXD_IOSTANDARD	"DEFAULT"
PXD_SLEW	"SLOW"
SENS_REFCLK_FREQUENCY	real 300 . 0
SENS_HIGH_PERFORMANCE_MODE	"FALSE"
SENS_PHASE_WIDTH	8
SENS_BANDWIDTH	"OPTIMIZED"
CLKIN_PERIOD_SENSOR	10 . 000
CLKFBOUT_MULT_SENSOR	8
CLKFBOUT_PHASE_SENSOR	0 . 000
IPCLK_PHASE	0 . 000
IPCLK2X_PHASE	0 . 000
BUF_IPCLK	"BUFR "
BUF_IPCLK2X	"BUFR "
SENS_DIVCLK_DIVIDE	1
SENS_REF_JITTER1	0 . 010
SENS_REF_JITTER2	0 . 010
SENS_SS_EN	"FALSE"
SENS_SS_MODE	"CENTER_HIGH"
SENS_SS_MOD_PERIOD	10000
STATUS_ALIVE_WIDTH	4

GENERATE
GENERATE [523]
GENERATE [777]
GENERATE [786]

Signals
wire[ 11 : 0 ]	pxd_out_pre
wire	vact_out_pre
reg[ 2 : 0 ]	irst_r
wire	ibpf
wire	ipclk_pre
wire	ipclk2x_pre
reg[ 31 : 0 ]	data_r
reg[ 3 : 0 ]	set_idelay
reg	set_ctrl_r
reg	set_status_r
reg[ 1 : 0 ]	set_width_r
wire	set_width_ipclk_w
reg	set_width_ipclk_r
wire	set_width_ipclk
reg	set_jtag_r
reg[LINE_WIDTH_BITS - 1 : 0 ]	line_width_m1
reg[LINE_WIDTH_BITS - 1 : 0 ]	line_width_m1_ipclk
reg	line_width_internal
reg	line_width_internal_ipclk
reg[LINE_WIDTH_BITS - 1 : 0 ]	hact_cntr
wire	clk_fb
wire[ 2 : 0 ]	set_pxd_delay
wire	set_other_delay
wire	ps_rdy
wire[ 7 : 0 ]	ps_out
wire	locked_pxd_mmcm
wire	clkin_pxd_stopped_mmcm
wire	clkfb_pxd_stopped_mmcm
reg	iaro_soft
wire	iaro
reg	iarst
reg	imrst
reg	rst_mmcm
reg[SENS_CTRL_QUADRANTS_WIDTH - 1 : 0 ]	quadrants
reg	ld_idelay
reg	sel_ext_clk
wire[ 25 : 0 ]	status
wire	cmd_we
wire[ 2 : 0 ]	cmd_a
wire[ 31 : 0 ]	cmd_data
wire	xfpgadone
wire	xfpgatdo
reg[ 7 : 0 ]	xfpgatdo_byte
wire	senspgmin
reg	xpgmen
reg	xfpgaprog
reg	xfpgatck
reg	xfpgatms
reg	xfpgatdi
wire	hact_ext
reg	hact_ext_r
reg	hact_r
reg	vact_r
reg	hact_r2
wire	vact_a_mclk
wire	hact_ext_a_mclk
wire	hact_a_mclk
reg	vact_alive
reg	hact_ext_alive
reg	hact_alive
reg[STATUS_ALIVE_WIDTH - 1 : 0 ]	status_alive
reg[ 1 : 0 ]	prst_with_sens_mrst
wire	async_prst_with_sens_mrst
wire	n_xfpgatdo
reg[ 1 : 0 ]	xpgmen_d
reg	force_senspgm

Module Instances
pulse_cross_clock::pulse_cross_clock_set_width_ipclk_i	Module pulse_cross_clock
cmd_deser::cmd_deser_sens_io_i	Module cmd_deser
status_generate::status_generate_sens_io_i	Module status_generate
pxd_single::pxd_pxd0_i	Module pxd_single
pxd_single::pxd_pxd1_i	Module pxd_single
pxd_single::pxd_pxd2_12_i	Module pxd_single [generate]
pxd_single::pxd_hact_i	Module pxd_single
pxd_single::pxd_vact_i	Module pxd_single
pxd_clock::pxd_clock_i	Module pxd_clock
oddr_ss::dclk_i	Module oddr_ss
iobuf::aro_tck_i	Module iobuf
iobuf::arst_tms_i	Module iobuf
iobuf::mrst_done_i	Module iobuf
iobuf::senspgm_i	Module iobuf
mpullup::i_mrst_pullup	Module mpullup
mpullup::i_senspgm_pullup	Module mpullup
mmcm_phase_cntr::mmcm_phase_cntr_i	Module mmcm_phase_cntr
BUFG::clk1x_i	Module BUFG [generate]
BUFH::clk1x_i	Module BUFH [generate]
BUFR::clk1x_i	Module BUFR [generate]
BUFMR::clk1x_i	Module BUFMR [generate]
BUFIO::clk1x_i	Module BUFIO [generate]
BUFG::clk2x_i	Module BUFG [generate]
BUFH::clk2x_i	Module BUFH [generate]
BUFR::clk2x_i	Module BUFR [generate]
BUFMR::clk2x_i	Module BUFMR [generate]
BUFIO::clk2x_i	Module BUFIO [generate]
pulse_cross_clock::pulse_cross_clock_vact_a_mclk_i	Module pulse_cross_clock
pulse_cross_clock::pulse_cross_clock_hact_ext_a_mclk_i	Module pulse_cross_clock
pulse_cross_clock::pulse_cross_clock_hact_a_mclk_i	Module pulse_cross_clock