Static Public Member Functions

Always Constructs
ALWAYS_366	( pclk )
ALWAYS_367	( mclk )
ALWAYS_368	( pclk )
ALWAYS_369	( pclk )
ALWAYS_370	( pclk )
ALWAYS_371	( mclk )
ALWAYS_372	( pclk )

Public Attributes

Inputs
mrst
prst
pclk
sof
eof
hact
hist_di	[ 7 : 0 ]
mclk
hist_en
hist_rst
hist_grant
cmd_ad	[ 7 : 0 ]
cmd_stb
debug_sl
debug_di

Outputs
hist_rq
hist_do	[ 31 : 0 ]
hist_dv	reg
debug_do

Parameters
HISTOGRAM_RAM_MODE	"BUF32"
HISTOGRAM_ADDR	'h33c
HISTOGRAM_ADDR_MASK	'h7fe
HISTOGRAM_LEFT_TOP	'h0
HISTOGRAM_WIDTH_HEIGHT	'h1
7492
7493
HIST_WIDTH	(HISTOGRAM_RAM_MODE == "BUF18") ? 18 : 32

GENERATE
GENERATE [514]

Signals
reg	hist_bank_pclk
reg[ 8 : 0 ]	hist_rwaddr_even
reg[ 8 : 0 ]	hist_rwaddr_odd
reg	hist_bank_mclk
wire	set_left_top_w
wire	set_width_height_w
wire[ 1 : 0 ]	pio_addr
wire[ 31 : 0 ]	pio_data
wire	pio_stb
reg[ 31 : 0 ]	lt_mclk
reg[ 31 : 0 ]	wh_mclk
reg[ 15 : 0 ]	width_m1
reg[ 15 : 0 ]	height_m1
reg[ 15 : 0 ]	left
reg[ 15 : 0 ]	top
reg	hist_en_pclk
reg	hist_rst_pclk
reg	en
reg	en_new
reg	en_mclk
wire	set_left_top_pclk
wire	set_width_height_pclk
reg	odd_pix
reg[ 1 : 0 ]	bayer_pclk
reg[ 1 : 0 ]	hact_d
reg	top_margin
reg	hist_done
wire	hist_done_mclk
reg	vert_woi
reg	left_margin
reg[ 6 : 0 ]	hor_woi
reg[ 15 : 0 ]	vcntr
reg[ 15 : 0 ]	hcntr
wire	vcntr_zero_w
wire	hcntr_zero_w
reg	hist_out
reg	hist_out_d
reg[ 2 : 0 ]	hist_re
reg	hist_re_even
reg	hist_re_odd
reg[ 9 : 0 ]	hist_raddr
reg	hist_rq_r
wire	hist_xfer_done_mclk
wire	hist_xfer_done
reg	hist_xfer_busy
reg	wait_readout
reg[ 15 : 0 ]	debug_line_cntr
reg[ 15 : 0 ]	debug_lines
wire	line_start_w
reg	pre_first_line
reg	frame_active
reg[ 6 : 0 ]	memen_even
reg[ 6 : 0 ]	memen_odd
wire	set_ra_even
wire	regen_even
wire	set_wa_even
wire	we_even
wire	set_ra_odd
wire	regen_odd
wire	set_wa_odd
wire	we_odd
reg	rwen_even
reg	rwen_odd
wire[ 7 : 0 ]	px_d0
wire[ 7 : 0 ]	px_d2
wire[ 7 : 0 ]	px_d4
wire[ 7 : 0 ]	px_d5
reg[HIST_WIDTH - 1 : 0 ]	r0
reg[HIST_WIDTH - 1 : 0 ]	r1
reg	r1_sat
reg[HIST_WIDTH - 1 : 0 ]	r2
reg[HIST_WIDTH - 1 : 0 ]	r3
wire[HIST_WIDTH - 1 : 0 ]	hist_new_even
wire[HIST_WIDTH - 1 : 0 ]	hist_new_odd
reg[ 3 : 0 ]	r_load
reg	r0_sel
reg	eq_prev_prev
wire	eq_prev_prev_d2
reg	eq_prev
wire	eq_prev_d3
reg	en_rq_start

Module Instances
debug_slave::debug_slave_i	Module debug_slave
cmd_deser::cmd_deser_sens_histogram_i	Module cmd_deser
dly_16::dly_16_px_dly0_i	Module dly_16
dly_16::dly_16_px_dly2_i	Module dly_16
dly_16::dly_16_px_dly4_i	Module dly_16
dly_16::dly_16_px_dly5_i	Module dly_16
dly_16::dly_16_eq_prev_prev_d2_i	Module dly_16
dly_16::dly_16_eq_prev_d3_i	Module dly_16
pulse_cross_clock::pulse_cross_clock_lt_i	Module pulse_cross_clock
pulse_cross_clock::pulse_cross_clock_wh_i	Module pulse_cross_clock
pulse_cross_clock::pulse_cross_clock_hist_done_i	Module pulse_cross_clock
pulse_cross_clock::pulse_cross_clock_hist_xfer_done_i	Module pulse_cross_clock
sens_hist_ram_snglclk_32::sens_hist_ram_snglclk_32_i	Module sens_hist_ram_snglclk_32 [generate]
sens_hist_ram_snglclk_18::sens_hist_ram_snglclk_18_i	Module sens_hist_ram_snglclk_18 [generate]