sens_hist_ram_snglclk_18 Module Reference

Inheritance diagram for sens_hist_ram_snglclk_18:

Collaboration diagram for sens_hist_ram_snglclk_18:

Static Public Member Functions

Always Constructs
ALWAYS_374	( mclk )

Public Attributes

Inputs
pclk
addr_a_even	[ 9 : 0 ]
addr_a_odd	[ 9 : 0 ]
data_in_a	[ 17 : 0 ]
en_a_even
en_a_odd
regen_a_even
regen_a_odd
we_a_even
we_a_odd
mclk
addr_b	[ 9 : 0 ]
re_even
re_odd

Outputs
data_out_a_even	[ 17 : 0 ]
data_out_a_odd	[ 17 : 0 ]
data_out_b	reg [ 31 : 0 ]

Signals
reg	re_even_d
reg	re_odd_d
reg	odd
wire[ 17 : 0 ]	data_out_b_w_even
wire[ 17 : 0 ]	data_out_b_w_odd

Module Instances
ram18tp_var_w_var_r::ramt_var_w_var_r_even_i	Module ram18tp_var_w_var_r
ram18tp_var_w_var_r::ramt_var_w_var_r_odd_i	Module ram18tp_var_w_var_r

Detailed Description

Definition at line 644 of file sens_histogram_snglclk.v.

Member Function Documentation

ALWAYS_374 (   mclk   )

Always Construct

Definition at line 669 of file sens_histogram_snglclk.v.

Member Data Documentation

pclk

Input

Definition at line 645 of file sens_histogram_snglclk.v.

addr_a_even [ 9 : 0 ]

Input

Definition at line 646 of file sens_histogram_snglclk.v.

addr_a_odd [ 9 : 0 ]

Input

Definition at line 647 of file sens_histogram_snglclk.v.

data_in_a [ 17 : 0 ]

Input

Definition at line 648 of file sens_histogram_snglclk.v.

data_out_a_even [ 17 : 0 ]

Output

Definition at line 649 of file sens_histogram_snglclk.v.

data_out_a_odd [ 17 : 0 ]

Output

Definition at line 650 of file sens_histogram_snglclk.v.

en_a_even

Input

Definition at line 651 of file sens_histogram_snglclk.v.

en_a_odd

Input

Definition at line 652 of file sens_histogram_snglclk.v.

regen_a_even

Input

Definition at line 653 of file sens_histogram_snglclk.v.

regen_a_odd

Input

Definition at line 654 of file sens_histogram_snglclk.v.

we_a_even

Input

Definition at line 655 of file sens_histogram_snglclk.v.

we_a_odd

Input

Definition at line 656 of file sens_histogram_snglclk.v.

mclk

Input

Definition at line 658 of file sens_histogram_snglclk.v.

addr_b [ 9 : 0 ]

Input

Definition at line 659 of file sens_histogram_snglclk.v.

data_out_b reg [ 31 : 0 ]

Output

Definition at line 660 of file sens_histogram_snglclk.v.

re_even

Input

Definition at line 661 of file sens_histogram_snglclk.v.

re_odd

Input

Definition at line 662 of file sens_histogram_snglclk.v.

re_even_d

Signal

Definition at line 664 of file sens_histogram_snglclk.v.

re_odd_d

Signal

Definition at line 665 of file sens_histogram_snglclk.v.

odd

Signal

Definition at line 666 of file sens_histogram_snglclk.v.

data_out_b_w_even

Signal

Definition at line 667 of file sens_histogram_snglclk.v.

data_out_b_w_odd

Signal

Definition at line 668 of file sens_histogram_snglclk.v.

ram18tp_var_w_var_r ramt_var_w_var_r_even_i

Module Instance

Definition at line 676 of file sens_histogram_snglclk.v.

ram18tp_var_w_var_r ramt_var_w_var_r_odd_i

Module Instance

Definition at line 700 of file sens_histogram_snglclk.v.

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The documentation for this Module was generated from the following files:

• sensor/sens_histogram_snglclk.v