sens_histogram_snglclk Member List

This is the complete list of members for sens_histogram_snglclk, including all inherited members.

SHIFT_WIDTH	debug_slave	Parameter
READ_WIDTH	debug_slave	Parameter
WRITE_WIDTH	debug_slave	Parameter
DEBUG_CMD_LATENCY	debug_slave	Parameter
mclk	debug_slave	Input
mrst	debug_slave	Input
debug_di	debug_slave	Input
debug_sl	debug_slave	Input
debug_do	debug_slave	Output
rd_data	debug_slave	Input
wr_data	debug_slave	Output
stb	debug_slave	Output
data_sr	debug_slave	Signal
cmd	debug_slave	Signal
cmd_reg	debug_slave	Signal
cmd_reg_dly	debug_slave	Signal
ext_rdata	debug_slave	Signal
WIDTH	dly_16	Parameter
clk	dly_16	Input
rst	dly_16	Input
dly	dly_16	Input
din	dly_16	Input
dout	dly_16	Output
EXTRA_DLY	pulse_cross_clock	Parameter
rst	pulse_cross_clock	Input
src_clk	pulse_cross_clock	Input
dst_clk	pulse_cross_clock	Input
in_pulse	pulse_cross_clock	Input
out_pulse	pulse_cross_clock	Output
busy	pulse_cross_clock	Output
EXTRA_DLY_SAFE	pulse_cross_clock	Parameter
in_reg	pulse_cross_clock	Signal
out_reg	pulse_cross_clock	Signal
busy_r	pulse_cross_clock	Signal
HISTOGRAM_RAM_MODE	sens_histogram_snglclk
HISTOGRAM_ADDR	sens_histogram_snglclk
HISTOGRAM_ADDR_MASK	sens_histogram_snglclk
HISTOGRAM_LEFT_TOP	sens_histogram_snglclk
HISTOGRAM_WIDTH_HEIGHT	sens_histogram_snglclk
7492	sens_histogram_snglclk
7493	sens_histogram_snglclk
mrst	sens_histogram_snglclk
prst	sens_histogram_snglclk
pclk	sens_histogram_snglclk
sof	sens_histogram_snglclk
eof	sens_histogram_snglclk
hact	sens_histogram_snglclk
hist_di	sens_histogram_snglclk
mclk	sens_histogram_snglclk
hist_en	sens_histogram_snglclk
hist_rst	sens_histogram_snglclk
hist_rq	sens_histogram_snglclk
hist_grant	sens_histogram_snglclk
hist_do	sens_histogram_snglclk
hist_dv	sens_histogram_snglclk
cmd_ad	sens_histogram_snglclk
cmd_stb	sens_histogram_snglclk
debug_do	sens_histogram_snglclk
debug_sl	sens_histogram_snglclk
debug_di	sens_histogram_snglclk
HIST_WIDTH	sens_histogram_snglclk
hist_bank_pclk	sens_histogram_snglclk
hist_rwaddr_even	sens_histogram_snglclk
hist_rwaddr_odd	sens_histogram_snglclk
hist_bank_mclk	sens_histogram_snglclk
set_left_top_w	sens_histogram_snglclk
set_width_height_w	sens_histogram_snglclk
pio_addr	sens_histogram_snglclk
pio_data	sens_histogram_snglclk
pio_stb	sens_histogram_snglclk
lt_mclk	sens_histogram_snglclk
wh_mclk	sens_histogram_snglclk
width_m1	sens_histogram_snglclk
height_m1	sens_histogram_snglclk
left	sens_histogram_snglclk
top	sens_histogram_snglclk
hist_en_pclk	sens_histogram_snglclk
hist_rst_pclk	sens_histogram_snglclk
en	sens_histogram_snglclk
en_new	sens_histogram_snglclk
en_mclk	sens_histogram_snglclk
set_left_top_pclk	sens_histogram_snglclk
set_width_height_pclk	sens_histogram_snglclk
odd_pix	sens_histogram_snglclk
bayer_pclk	sens_histogram_snglclk
hact_d	sens_histogram_snglclk
top_margin	sens_histogram_snglclk
hist_done	sens_histogram_snglclk
hist_done_mclk	sens_histogram_snglclk
vert_woi	sens_histogram_snglclk
left_margin	sens_histogram_snglclk
hor_woi	sens_histogram_snglclk
vcntr	sens_histogram_snglclk
hcntr	sens_histogram_snglclk
vcntr_zero_w	sens_histogram_snglclk
hcntr_zero_w	sens_histogram_snglclk
hist_out	sens_histogram_snglclk
hist_out_d	sens_histogram_snglclk
hist_re	sens_histogram_snglclk
hist_re_even	sens_histogram_snglclk
hist_re_odd	sens_histogram_snglclk
hist_raddr	sens_histogram_snglclk
hist_rq_r	sens_histogram_snglclk
hist_xfer_done_mclk	sens_histogram_snglclk
hist_xfer_done	sens_histogram_snglclk
hist_xfer_busy	sens_histogram_snglclk
wait_readout	sens_histogram_snglclk
debug_line_cntr	sens_histogram_snglclk
debug_lines	sens_histogram_snglclk
line_start_w	sens_histogram_snglclk
pre_first_line	sens_histogram_snglclk
frame_active	sens_histogram_snglclk
memen_even	sens_histogram_snglclk
memen_odd	sens_histogram_snglclk
set_ra_even	sens_histogram_snglclk
regen_even	sens_histogram_snglclk
set_wa_even	sens_histogram_snglclk
we_even	sens_histogram_snglclk
set_ra_odd	sens_histogram_snglclk
regen_odd	sens_histogram_snglclk
set_wa_odd	sens_histogram_snglclk
we_odd	sens_histogram_snglclk
rwen_even	sens_histogram_snglclk
rwen_odd	sens_histogram_snglclk
px_d0	sens_histogram_snglclk
px_d2	sens_histogram_snglclk
px_d4	sens_histogram_snglclk
px_d5	sens_histogram_snglclk
r0	sens_histogram_snglclk
r1	sens_histogram_snglclk
r1_sat	sens_histogram_snglclk
r2	sens_histogram_snglclk
r3	sens_histogram_snglclk
hist_new_even	sens_histogram_snglclk
hist_new_odd	sens_histogram_snglclk
r_load	sens_histogram_snglclk
r0_sel	sens_histogram_snglclk
eq_prev_prev	sens_histogram_snglclk
eq_prev_prev_d2	sens_histogram_snglclk
eq_prev	sens_histogram_snglclk
eq_prev_d3	sens_histogram_snglclk
en_rq_start	sens_histogram_snglclk
pclk	sens_hist_ram_snglclk_32	Input
addr_a_even	sens_hist_ram_snglclk_32	Input
addr_a_odd	sens_hist_ram_snglclk_32	Input
data_in_a	sens_hist_ram_snglclk_32	Input
data_out_a_even	sens_hist_ram_snglclk_32	Output
data_out_a_odd	sens_hist_ram_snglclk_32	Output
en_a_even	sens_hist_ram_snglclk_32	Input
en_a_odd	sens_hist_ram_snglclk_32	Input
regen_a_even	sens_hist_ram_snglclk_32	Input
regen_a_odd	sens_hist_ram_snglclk_32	Input
we_a_even	sens_hist_ram_snglclk_32	Input
we_a_odd	sens_hist_ram_snglclk_32	Input
mclk	sens_hist_ram_snglclk_32	Input
addr_b	sens_hist_ram_snglclk_32	Input
data_out_b	sens_hist_ram_snglclk_32	Output
re_even	sens_hist_ram_snglclk_32	Input
re_odd	sens_hist_ram_snglclk_32	Input
re_even_d	sens_hist_ram_snglclk_32	Signal
re_odd_d	sens_hist_ram_snglclk_32	Signal
odd	sens_hist_ram_snglclk_32	Signal
data_out_b_w_even	sens_hist_ram_snglclk_32	Signal
data_out_b_w_odd	sens_hist_ram_snglclk_32	Signal
pclk	sens_hist_ram_snglclk_18	Input
addr_a_even	sens_hist_ram_snglclk_18	Input
addr_a_odd	sens_hist_ram_snglclk_18	Input
data_in_a	sens_hist_ram_snglclk_18	Input
data_out_a_even	sens_hist_ram_snglclk_18	Output
data_out_a_odd	sens_hist_ram_snglclk_18	Output
en_a_even	sens_hist_ram_snglclk_18	Input
en_a_odd	sens_hist_ram_snglclk_18	Input
regen_a_even	sens_hist_ram_snglclk_18	Input
regen_a_odd	sens_hist_ram_snglclk_18	Input
we_a_even	sens_hist_ram_snglclk_18	Input
we_a_odd	sens_hist_ram_snglclk_18	Input
mclk	sens_hist_ram_snglclk_18	Input
addr_b	sens_hist_ram_snglclk_18	Input
data_out_b	sens_hist_ram_snglclk_18	Output
re_even	sens_hist_ram_snglclk_18	Input
re_odd	sens_hist_ram_snglclk_18	Input
re_even_d	sens_hist_ram_snglclk_18	Signal
re_odd_d	sens_hist_ram_snglclk_18	Signal
odd	sens_hist_ram_snglclk_18	Signal
data_out_b_w_even	sens_hist_ram_snglclk_18	Signal
data_out_b_w_odd	sens_hist_ram_snglclk_18	Signal
ADDR	cmd_deser	Parameter
ADDR_MASK	cmd_deser	Parameter
NUM_CYCLES	cmd_deser	Parameter
ADDR_WIDTH	cmd_deser	Parameter
DATA_WIDTH	cmd_deser	Parameter
ADDR1	cmd_deser	Parameter
ADDR_MASK1	cmd_deser	Parameter
ADDR2	cmd_deser	Parameter
ADDR_MASK2	cmd_deser	Parameter
WE_EARLY	cmd_deser	Parameter
rst	cmd_deser	Input
clk	cmd_deser	Input
srst	cmd_deser	Input
ad	cmd_deser	Input
stb	cmd_deser	Input
addr	cmd_deser	Output
data	cmd_deser	Output
we	cmd_deser	Output
WE_WIDTH	cmd_deser	Parameter
ALWAYS_366 pclk	sens_histogram_snglclk	Always Construct
ALWAYS_367 mclk	sens_histogram_snglclk	Always Construct
ALWAYS_368 pclk	sens_histogram_snglclk	Always Construct
ALWAYS_369 pclk	sens_histogram_snglclk	Always Construct
ALWAYS_370 pclk	sens_histogram_snglclk	Always Construct
ALWAYS_371 mclk	sens_histogram_snglclk	Always Construct
ALWAYS_372 pclk	sens_histogram_snglclk	Always Construct
ALWAYS_373 mclk	sens_hist_ram_snglclk_32	Always Construct
ALWAYS_374 mclk	sens_hist_ram_snglclk_18	Always Construct
ALWAYS_497 mclk	debug_slave	Always Construct
ALWAYS_532 src_clk or rst	pulse_cross_clock	Always Construct
ALWAYS_533 dst_clk	pulse_cross_clock	Always Construct
cmd_deser	sens_histogram_snglclk
cmd_deser_dual	cmd_deser	Module Instance
cmd_deser_multi	cmd_deser	Module Instance
cmd_deser_single	cmd_deser	Module Instance
debug_slave	sens_histogram_snglclk
dly01_16	dly_16	Module Instance
dly_16	sens_histogram_snglclk
dly_16	sens_histogram_snglclk
dly_16	sens_histogram_snglclk
dly_16	sens_histogram_snglclk
dly_16	sens_histogram_snglclk
dly_16	sens_histogram_snglclk
GENERATE [50]	dly_16	GENERATE
GENERATE [514]	sens_histogram_snglclk
GENERATE [63]	cmd_deser	GENERATE
pulse_cross_clock	sens_histogram_snglclk
pulse_cross_clock	sens_histogram_snglclk
pulse_cross_clock	sens_histogram_snglclk
pulse_cross_clock	sens_histogram_snglclk
ram18tp_var_w_var_r	sens_hist_ram_snglclk_18	Module Instance
ram18tp_var_w_var_r	sens_hist_ram_snglclk_18	Module Instance
ramt_var_w_var_r	sens_hist_ram_snglclk_32	Module Instance
ramt_var_w_var_r	sens_hist_ram_snglclk_32	Module Instance
sens_hist_ram_snglclk_18	sens_histogram_snglclk
sens_hist_ram_snglclk_32	sens_histogram_snglclk