memctrl16 Member List

This is the complete list of members for memctrl16, including all inherited members.

clk	dly01_16	Input
rst	dly01_16	Input
dly	dly01_16	Input
din	dly01_16	Input
dout	dly01_16	Output
sr	dly01_16	Signal
WIDTH	dly_16	Parameter
clk	dly_16	Input
rst	dly_16	Input
dly	dly_16	Input
din	dly_16	Input
dout	dly_16	Output
CHN_NUMBER	mcont_common_chnbuf_reg	Parameter
rst	mcont_common_chnbuf_reg	Input
clk	mcont_common_chnbuf_reg	Input
ext_buf_rchn	mcont_common_chnbuf_reg	Input
ext_buf_rrefresh	mcont_common_chnbuf_reg	Input
ext_buf_page_nxt	mcont_common_chnbuf_reg	Input
seq_done	mcont_common_chnbuf_reg	Input
ext_buf_run	mcont_common_chnbuf_reg	Input
buf_done	mcont_common_chnbuf_reg	Output
page_nxt	mcont_common_chnbuf_reg	Output
buf_run	mcont_common_chnbuf_reg	Output
buf_chn_sel	mcont_common_chnbuf_reg	Signal
CHN_NUMBER	mcont_from_chnbuf_reg	Parameter
CHN_LATENCY	mcont_from_chnbuf_reg	Parameter
rst	mcont_from_chnbuf_reg	Input
clk	mcont_from_chnbuf_reg	Input
ext_buf_rd	mcont_from_chnbuf_reg	Input
ext_buf_rchn	mcont_from_chnbuf_reg	Input
ext_buf_rrefresh	mcont_from_chnbuf_reg	Input
ext_buf_rpage_nxt	mcont_from_chnbuf_reg	Input
ext_buf_rdata	mcont_from_chnbuf_reg	Output
buf_rd_chn	mcont_from_chnbuf_reg	Output
rpage_nxt	mcont_from_chnbuf_reg	Output
buf_rdata_chn	mcont_from_chnbuf_reg	Input
buf_rdata_chn_r	mcont_from_chnbuf_reg	Signal
buf_chn_sel	mcont_from_chnbuf_reg	Signal
latency_reg	mcont_from_chnbuf_reg	Signal
CHN_NUMBER	mcont_to_chnbuf_reg	Parameter
rst	mcont_to_chnbuf_reg	Input
clk	mcont_to_chnbuf_reg	Input
ext_buf_wr	mcont_to_chnbuf_reg	Input
ext_buf_wpage_nxt	mcont_to_chnbuf_reg	Input
ext_buf_wchn	mcont_to_chnbuf_reg	Input
ext_buf_wrefresh	mcont_to_chnbuf_reg	Input
ext_buf_wrun	mcont_to_chnbuf_reg	Input
ext_buf_wdata	mcont_to_chnbuf_reg	Input
buf_wr_chn	mcont_to_chnbuf_reg	Output
buf_wpage_nxt_chn	mcont_to_chnbuf_reg	Output
buf_run	mcont_to_chnbuf_reg	Output
buf_wdata_chn	mcont_to_chnbuf_reg	Output
buf_chn_sel	mcont_to_chnbuf_reg	Signal
rst_nclk	mcont_to_chnbuf_reg	Signal
status_generate.STATUS_REG_ADDR	status_generate	Parameter
mcontr_sequencer.STATUS_REG_ADDR	status_generate	Parameter
status_generate.PAYLOAD_BITS	status_generate	Parameter
mcontr_sequencer.PAYLOAD_BITS	status_generate	Parameter
status_generate.REGISTER_STATUS	status_generate	Parameter
mcontr_sequencer.REGISTER_STATUS	status_generate	Parameter
status_generate.EXTRA_WORDS	status_generate	Parameter
mcontr_sequencer.EXTRA_WORDS	status_generate	Parameter
status_generate.EXTRA_REG_ADDR	status_generate	Parameter
mcontr_sequencer.EXTRA_REG_ADDR	status_generate	Parameter
status_generate.rst	status_generate	Input
mcontr_sequencer.rst	status_generate	Input
status_generate.clk	status_generate	Input
mcontr_sequencer.clk	status_generate	Input
status_generate.srst	status_generate	Input
mcontr_sequencer.srst	status_generate	Input
status_generate.we	status_generate	Input
mcontr_sequencer.we	status_generate	Input
status_generate.wd	status_generate	Input
mcontr_sequencer.wd	status_generate	Input
status_generate.status	status_generate	Input
mcontr_sequencer.status	status_generate	Input
status_generate.ad	status_generate	Output
mcontr_sequencer.ad	status_generate	Output
status_generate.rq	status_generate	Output
mcontr_sequencer.rq	status_generate	Output
status_generate.start	status_generate	Input
mcontr_sequencer.start	status_generate	Input
status_generate.STATUS_BITS	status_generate	Parameter
mcontr_sequencer.STATUS_BITS	status_generate	Parameter
status_generate.ALL_BITS	status_generate	Parameter
mcontr_sequencer.ALL_BITS	status_generate	Parameter
FIFO_TYPE	status_router2	Parameter
rst	status_router2	Input
clk	status_router2	Input
srst	status_router2	Input
db_in0	status_router2	Input
rq_in0	status_router2	Input
start_in0	status_router2	Output
db_in1	status_router2	Input
rq_in1	status_router2	Input
start_in1	status_router2	Output
db_out	status_router2	Output
rq_out	status_router2	Output
start_out	status_router2	Input
rq_in	status_router2	Signal
start_rcv	status_router2	Signal
rcv_rest_r	status_router2	Signal
fifo_half_full	status_router2	Signal
fifo0_out	status_router2	Signal
fifo1_out	status_router2	Signal
fifo_last_byte	status_router2	Signal
fifo_nempty_pre	status_router2	Signal
fifo_nempty	status_router2	Signal
fifo_re	status_router2	Signal
next_chn	status_router2	Signal
current_chn_r	status_router2	Signal
snd_rest_r	status_router2	Signal
snd_pre_start	status_router2	Signal
snd_last_byte	status_router2	Signal
chn_sel_w	status_router2	Signal
early_chn	status_router2	Signal
set_other_only_w	status_router2	Signal
mrst	ddr_refresh	Input
clk	ddr_refresh	Input
en	ddr_refresh	Input
refresh_period	ddr_refresh	Input
set	ddr_refresh	Input
want	ddr_refresh	Output
need	ddr_refresh	Output
grant	ddr_refresh	Input
pre_div	ddr_refresh	Signal
pending_rq	ddr_refresh	Signal
period_cntr	ddr_refresh	Signal
cry	ddr_refresh	Signal
over	ddr_refresh	Signal
refresh_due	ddr_refresh	Signal
en_refresh	ddr_refresh	Signal
en_r	ddr_refresh	Signal
DLY_LD	memctrl16
DLY_LD_MASK	memctrl16
MCONTR_PHY_0BIT_ADDR	memctrl16
MCONTR_PHY_0BIT_ADDR_MASK	memctrl16
MCONTR_PHY_0BIT_DLY_SET	memctrl16
MCONTR_PHY_0BIT_CMDA_EN	memctrl16
MCONTR_PHY_0BIT_SDRST_ACT	memctrl16
MCONTR_PHY_0BIT_CKE_EN	memctrl16
MCONTR_PHY_0BIT_DCI_RST	memctrl16
MCONTR_PHY_0BIT_DLY_RST	memctrl16
MCONTR_TOP_0BIT_ADDR	memctrl16
MCONTR_TOP_0BIT_ADDR_MASK	memctrl16
MCONTR_TOP_0BIT_MCONTR_EN	memctrl16
MCONTR_TOP_0BIT_REFRESH_EN	memctrl16
MCONTR_PHY_16BIT_ADDR	memctrl16
MCONTR_PHY_16BIT_ADDR_MASK	memctrl16
MCONTR_PHY_16BIT_PATTERNS	memctrl16
MCONTR_PHY_16BIT_PATTERNS_TRI	memctrl16
MCONTR_PHY_16BIT_WBUF_DELAY	memctrl16
MCONTR_PHY_16BIT_EXTRA	memctrl16
MCONTR_PHY_STATUS_CNTRL	memctrl16
MCONTR_ARBIT_ADDR	memctrl16
MCONTR_ARBIT_ADDR_MASK	memctrl16
MCONTR_TOP_16BIT_ADDR	memctrl16
MCONTR_TOP_16BIT_ADDR_MASK	memctrl16
MCONTR_TOP_16BIT_CHN_EN	memctrl16
MCONTR_TOP_16BIT_REFRESH_PERIOD	memctrl16
MCONTR_TOP_16BIT_REFRESH_ADDRESS	memctrl16
MCONTR_TOP_16BIT_STATUS_CNTRL	memctrl16
MCONTR_PHY_STATUS_REG_ADDR	memctrl16
MCONTR_TOP_STATUS_REG_ADDR	memctrl16
CHNBUF_READ_LATENCY	memctrl16
DFLT_DQS_PATTERN	memctrl16
DFLT_DQM_PATTERN	memctrl16
DFLT_DQ_TRI_ON_PATTERN	memctrl16
DFLT_DQ_TRI_OFF_PATTERN	memctrl16
DFLT_DQS_TRI_ON_PATTERN	memctrl16
DFLT_DQS_TRI_OFF_PATTERN	memctrl16
DFLT_WBUF_DELAY	memctrl16
DFLT_INV_CLK_DIV	memctrl16
DFLT_CHN_EN	memctrl16
DFLT_REFRESH_ADDR	memctrl16
DFLT_REFRESH_PERIOD	memctrl16
ADDRESS_NUMBER	memctrl16
PHASE_WIDTH	memctrl16
SLEW_DQ	memctrl16
SLEW_DQS	memctrl16
SLEW_CMDA	memctrl16
SLEW_CLK	memctrl16
IBUF_LOW_PWR	memctrl16
REFCLK_FREQUENCY	memctrl16
HIGH_PERFORMANCE_MODE	memctrl16
CLKIN_PERIOD	memctrl16
CLKFBOUT_MULT	memctrl16
DIVCLK_DIVIDE	memctrl16
CLKFBOUT_USE_FINE_PS	memctrl16
CLKFBOUT_PHASE	memctrl16
SDCLK_PHASE	memctrl16
CLK_PHASE	memctrl16
CLK_DIV_PHASE	memctrl16
MCLK_PHASE	memctrl16
REF_JITTER1	memctrl16
SS_EN	memctrl16
SS_MODE	memctrl16
SS_MOD_PERIOD	memctrl16
CMD_PAUSE_BITS	memctrl16
CMD_DONE_BIT	memctrl16
rst_in	memctrl16
clk_in	memctrl16
mclk	memctrl16
mrst	memctrl16
locked	memctrl16
ref_clk	memctrl16
idelay_ctrl_reset	memctrl16
cmd_ad	memctrl16
cmd_stb	memctrl16
status_ad	memctrl16
status_rq	memctrl16
status_start	memctrl16
cmd0_clk	memctrl16
cmd0_we	memctrl16
cmd0_addr	memctrl16
cmd0_data	memctrl16
seq_data	memctrl16
seq_wr	memctrl16
seq_set	memctrl16
want_rq0	memctrl16
need_rq0	memctrl16
channel_pgm_en0	memctrl16
reject0	memctrl16
seq_done0	memctrl16
page_nxt_chn0	memctrl16
buf_run0	memctrl16
buf_wr_chn0	memctrl16
buf_wpage_nxt_chn0	memctrl16
buf_wdata_chn0	memctrl16
buf_wrun0	memctrl16
buf_rd_chn0	memctrl16
buf_rpage_nxt_chn0	memctrl16
buf_rdata_chn0	memctrl16
want_rq1	memctrl16
need_rq1	memctrl16
channel_pgm_en1	memctrl16
reject1	memctrl16
seq_done1	memctrl16
page_nxt_chn1	memctrl16
buf_run1	memctrl16
buf_wr_chn1	memctrl16
buf_wpage_nxt_chn1	memctrl16
buf_wdata_chn1	memctrl16
buf_wrun1	memctrl16
buf_rd_chn1	memctrl16
buf_rpage_nxt_chn1	memctrl16
buf_rdata_chn1	memctrl16
want_rq2	memctrl16
need_rq2	memctrl16
channel_pgm_en2	memctrl16
reject2	memctrl16
seq_done2	memctrl16
page_nxt_chn2	memctrl16
buf_run2	memctrl16
buf_wr_chn2	memctrl16
buf_wpage_nxt_chn2	memctrl16
buf_wdata_chn2	memctrl16
buf_wrun2	memctrl16
buf_rd_chn2	memctrl16
buf_rpage_nxt_chn2	memctrl16
buf_rdata_chn2	memctrl16
want_rq3	memctrl16
need_rq3	memctrl16
channel_pgm_en3	memctrl16
reject3	memctrl16
seq_done3	memctrl16
page_nxt_chn3	memctrl16
buf_run3	memctrl16
buf_wr_chn3	memctrl16
buf_wpage_nxt_chn3	memctrl16
buf_wdata_chn3	memctrl16
buf_wrun3	memctrl16
buf_rd_chn3	memctrl16
buf_rpage_nxt_chn3	memctrl16
buf_rdata_chn3	memctrl16
want_rq4	memctrl16
need_rq4	memctrl16
channel_pgm_en4	memctrl16
reject4	memctrl16
seq_done4	memctrl16
page_nxt_chn4	memctrl16
buf_run4	memctrl16
buf_wr_chn4	memctrl16
buf_wpage_nxt_chn4	memctrl16
buf_wdata_chn4	memctrl16
buf_wrun4	memctrl16
buf_rd_chn4	memctrl16
buf_rpage_nxt_chn4	memctrl16
buf_rdata_chn4	memctrl16
want_rq8	memctrl16
need_rq8	memctrl16
channel_pgm_en8	memctrl16
reject8	memctrl16
seq_done8	memctrl16
page_nxt_chn8	memctrl16
buf_run8	memctrl16
buf_rd_chn8	memctrl16
buf_rpage_nxt_chn8	memctrl16
buf_rdata_chn8	memctrl16
want_rq9	memctrl16
need_rq9	memctrl16
channel_pgm_en9	memctrl16
reject9	memctrl16
seq_done9	memctrl16
page_nxt_chn9	memctrl16
buf_run9	memctrl16
buf_rd_chn9	memctrl16
buf_rpage_nxt_chn9	memctrl16
buf_rdata_chn9	memctrl16
want_rq10	memctrl16
need_rq10	memctrl16
channel_pgm_en10	memctrl16
reject10	memctrl16
seq_done10	memctrl16
page_nxt_chn10	memctrl16
buf_run10	memctrl16
buf_rd_chn10	memctrl16
buf_rpage_nxt_chn10	memctrl16
buf_rdata_chn10	memctrl16
want_rq11	memctrl16
need_rq11	memctrl16
channel_pgm_en11	memctrl16
reject11	memctrl16
seq_done11	memctrl16
page_nxt_chn11	memctrl16
buf_run11	memctrl16
buf_rd_chn11	memctrl16
buf_rpage_nxt_chn11	memctrl16
buf_rdata_chn11	memctrl16
want_rq12	memctrl16
need_rq12	memctrl16
channel_pgm_en12	memctrl16
reject12	memctrl16
seq_done12	memctrl16
page_nxt_chn12	memctrl16
buf_run12	memctrl16
buf_wr_chn12	memctrl16
buf_wpage_nxt_chn12	memctrl16
buf_wdata_chn12	memctrl16
buf_wrun12	memctrl16
want_rq13	memctrl16
need_rq13	memctrl16
channel_pgm_en13	memctrl16
reject13	memctrl16
seq_done13	memctrl16
page_nxt_chn13	memctrl16
buf_run13	memctrl16
buf_wr_chn13	memctrl16
buf_wpage_nxt_chn13	memctrl16
buf_wdata_chn13	memctrl16
buf_wrun13	memctrl16
want_rq14	memctrl16
need_rq14	memctrl16
channel_pgm_en14	memctrl16
reject14	memctrl16
seq_done14	memctrl16
page_nxt_chn14	memctrl16
buf_run14	memctrl16
buf_wr_chn14	memctrl16
buf_wpage_nxt_chn14	memctrl16
buf_wdata_chn14	memctrl16
buf_wrun14	memctrl16
want_rq15	memctrl16
need_rq15	memctrl16
channel_pgm_en15	memctrl16
reject15	memctrl16
seq_done15	memctrl16
page_nxt_chn15	memctrl16
buf_run15	memctrl16
buf_wr_chn15	memctrl16
buf_wpage_nxt_chn15	memctrl16
buf_wdata_chn15	memctrl16
buf_wrun15	memctrl16
SDRST	memctrl16
SDCLK	memctrl16
SDNCLK	memctrl16
SDA	memctrl16
SDBA	memctrl16
SDWE	memctrl16
SDRAS	memctrl16
SDCAS	memctrl16
SDCKE	memctrl16
SDODT	memctrl16
SDD	memctrl16
SDDML	memctrl16
DQSL	memctrl16
NDQSL	memctrl16
SDDMU	memctrl16
DQSU	memctrl16
NDQSU	memctrl16
tmp_debug	memctrl16
reject	memctrl16
ext_buf_rd	memctrl16
ext_buf_rpage_nxt	memctrl16
ext_buf_page_nxt	memctrl16
ext_buf_rchn	memctrl16
ext_buf_rrefresh	memctrl16
ext_buf_rrun	memctrl16
ext_buf_rdata	memctrl16
ext_buf_wr	memctrl16
ext_buf_wpage_nxt	memctrl16
ext_buf_wchn	memctrl16
ext_buf_wrefresh	memctrl16
ext_buf_wrun	memctrl16
ext_buf_wdata	memctrl16
want_rq	memctrl16
need_rq	memctrl16
status_ad_phy	memctrl16
status_rq_phy	memctrl16
status_start_phy	memctrl16
status_ad_mcontr	memctrl16
status_rq_mcontr	memctrl16
status_start_mcontr	memctrl16
set_status_w	memctrl16
en_schedul	memctrl16
need	memctrl16
grant	memctrl16
grant_chn	memctrl16
priority_addr	memctrl16
priority_data	memctrl16
priority_en	memctrl16
cmd_wr_chn	memctrl16
cmd_addr_cur	memctrl16
cmd_addr_start	memctrl16
grant_r	memctrl16
cmd_seq_set	memctrl16
cmd_seq_fill	memctrl16
cmd_seq_full	memctrl16
cmd_seq_need	memctrl16
cmd_seq_run	memctrl16
cmd_seq_chn	memctrl16
cmd_seq_refresh	memctrl16
cmd_seq_addr	memctrl16
sel_refresh_w	memctrl16
pre_run_seq_w	memctrl16
pre_run_chn_w	memctrl16
mcontr_reset	memctrl16
mcontr_enabled	memctrl16
sequencer_run_busy	memctrl16
sequencer_run_done	memctrl16
refresh_want	memctrl16
refresh_need	memctrl16
refresh_grant	memctrl16
refresh_en	memctrl16
refresh_period	memctrl16
refresh_addr	memctrl16
mcontr_en	memctrl16
mcontr_chn_en	memctrl16
chn_want_some	memctrl16
chn_need_some	memctrl16
chn_want_r	memctrl16
status_data	memctrl16
mcontr_0bit_addr	memctrl16
mcontr_0bit_we	memctrl16
mcontr_16bit_addr	memctrl16
mcontr_16bit_data	memctrl16
mcontr_16bit_we	memctrl16
set_chn_en_w	memctrl16
set_refresh_period_w	memctrl16
set_refresh_address_w	memctrl16
set_refresh_period	memctrl16
reject_r	memctrl16
ext_buf_rdata0	memctrl16
ext_buf_rdata1	memctrl16
ext_buf_rdata2	memctrl16
ext_buf_rdata3	memctrl16
ext_buf_rdata4	memctrl16
ext_buf_rdata8	memctrl16
ext_buf_rdata9	memctrl16
ext_buf_rdata10	memctrl16
ext_buf_rdata11	memctrl16
ext_buf_rchn_late	memctrl16
ext_buf_rd_late	memctrl16
EXT_READ_LATENCY	memctrl16
want_rq5	memctrl16
need_rq5	memctrl16
want_rq6	memctrl16
need_rq6	memctrl16
want_rq7	memctrl16
need_rq7	memctrl16
DLY_LD	mcontr_sequencer	Parameter
DLY_LD_MASK	mcontr_sequencer	Parameter
MCONTR_PHY_0BIT_ADDR	mcontr_sequencer	Parameter
MCONTR_PHY_0BIT_ADDR_MASK	mcontr_sequencer	Parameter
MCONTR_PHY_0BIT_DLY_SET	mcontr_sequencer	Parameter
MCONTR_PHY_0BIT_CMDA_EN	mcontr_sequencer	Parameter
MCONTR_PHY_0BIT_SDRST_ACT	mcontr_sequencer	Parameter
MCONTR_PHY_0BIT_CKE_EN	mcontr_sequencer	Parameter
MCONTR_PHY_0BIT_DCI_RST	mcontr_sequencer	Parameter
MCONTR_PHY_0BIT_DLY_RST	mcontr_sequencer	Parameter
MCONTR_PHY_STATUS_REG_ADDR	mcontr_sequencer	Parameter
MCONTR_PHY_16BIT_ADDR	mcontr_sequencer	Parameter
MCONTR_PHY_16BIT_ADDR_MASK	mcontr_sequencer	Parameter
MCONTR_PHY_16BIT_PATTERNS	mcontr_sequencer	Parameter
MCONTR_PHY_16BIT_PATTERNS_TRI	mcontr_sequencer	Parameter
MCONTR_PHY_16BIT_WBUF_DELAY	mcontr_sequencer	Parameter
MCONTR_PHY_16BIT_EXTRA	mcontr_sequencer	Parameter
MCONTR_PHY_STATUS_CNTRL	mcontr_sequencer	Parameter
DFLT_DQS_PATTERN	mcontr_sequencer	Parameter
DFLT_DQM_PATTERN	mcontr_sequencer	Parameter
DFLT_DQ_TRI_ON_PATTERN	mcontr_sequencer	Parameter
DFLT_DQ_TRI_OFF_PATTERN	mcontr_sequencer	Parameter
DFLT_DQS_TRI_ON_PATTERN	mcontr_sequencer	Parameter
DFLT_DQS_TRI_OFF_PATTERN	mcontr_sequencer	Parameter
DFLT_WBUF_DELAY	mcontr_sequencer	Parameter
DFLT_INV_CLK_DIV	mcontr_sequencer	Parameter
PHASE_WIDTH	mcontr_sequencer	Parameter
SLEW_DQ	mcontr_sequencer	Parameter
SLEW_DQS	mcontr_sequencer	Parameter
SLEW_CMDA	mcontr_sequencer	Parameter
SLEW_CLK	mcontr_sequencer	Parameter
IBUF_LOW_PWR	mcontr_sequencer	Parameter
REFCLK_FREQUENCY	mcontr_sequencer	Parameter
HIGH_PERFORMANCE_MODE	mcontr_sequencer	Parameter
CLKIN_PERIOD	mcontr_sequencer	Parameter
CLKFBOUT_MULT	mcontr_sequencer	Parameter
DIVCLK_DIVIDE	mcontr_sequencer	Parameter
CLKFBOUT_USE_FINE_PS	mcontr_sequencer	Parameter
CLKFBOUT_PHASE	mcontr_sequencer	Parameter
SDCLK_PHASE	mcontr_sequencer	Parameter
CLK_PHASE	mcontr_sequencer	Parameter
CLK_DIV_PHASE	mcontr_sequencer	Parameter
MCLK_PHASE	mcontr_sequencer	Parameter
REF_JITTER1	mcontr_sequencer	Parameter
SS_EN	mcontr_sequencer	Parameter
SS_MODE	mcontr_sequencer	Parameter
SS_MOD_PERIOD	mcontr_sequencer	Parameter
CMD_PAUSE_BITS	mcontr_sequencer	Parameter
CMD_DONE_BIT	mcontr_sequencer	Parameter
SDRST	mcontr_sequencer	Output
SDCLK	mcontr_sequencer	Output
SDNCLK	mcontr_sequencer	Output
SDA	mcontr_sequencer	Output
SDBA	mcontr_sequencer	Output
SDWE	mcontr_sequencer	Output
SDRAS	mcontr_sequencer	Output
SDCAS	mcontr_sequencer	Output
SDCKE	mcontr_sequencer	Output
SDODT	mcontr_sequencer	Output
SDD	mcontr_sequencer	Inout
SDDML	mcontr_sequencer	Output
DQSL	mcontr_sequencer	Inout
NDQSL	mcontr_sequencer	Inout
SDDMU	mcontr_sequencer	Output
DQSU	mcontr_sequencer	Inout
NDQSU	mcontr_sequencer	Inout
clk_in	mcontr_sequencer	Input
rst_in	mcontr_sequencer	Input
mclk	mcontr_sequencer	Output
mrst	mcontr_sequencer	Input
locked	mcontr_sequencer	Output
ref_clk	mcontr_sequencer	Input
idelay_ctrl_reset	mcontr_sequencer	Output
cmd0_clk	mcontr_sequencer	Input
cmd0_we	mcontr_sequencer	Input
cmd0_addr	mcontr_sequencer	Input
cmd0_data	mcontr_sequencer	Input
cmd1_clk	mcontr_sequencer	Input
cmd1_we	mcontr_sequencer	Input
cmd1_addr	mcontr_sequencer	Input
cmd1_data	mcontr_sequencer	Input
run_addr	mcontr_sequencer	Input
run_chn	mcontr_sequencer	Input
run_refresh	mcontr_sequencer	Input
run_seq	mcontr_sequencer	Input
run_done	mcontr_sequencer	Output
run_busy	mcontr_sequencer	Output
mcontr_reset	mcontr_sequencer	Output
cmd_ad	mcontr_sequencer	Input
cmd_stb	mcontr_sequencer	Input
status_ad	mcontr_sequencer	Output
status_rq	mcontr_sequencer	Output
status_start	mcontr_sequencer	Input
ext_buf_page_nxt	mcontr_sequencer	Output
ext_buf_rd	mcontr_sequencer	Output
ext_buf_rpage_nxt	mcontr_sequencer	Output
ext_buf_rchn	mcontr_sequencer	Output
ext_buf_rrefresh	mcontr_sequencer	Output
ext_buf_rrun	mcontr_sequencer	Output
ext_buf_rdata	mcontr_sequencer	Input
ext_buf_wr	mcontr_sequencer	Output
ext_buf_wpage_nxt	mcontr_sequencer	Output
ext_buf_wchn	mcontr_sequencer	Output
ext_buf_wrefresh	mcontr_sequencer	Output
ext_buf_wrun	mcontr_sequencer	Output
ext_buf_wdata	mcontr_sequencer	Output
tmp_debug	mcontr_sequencer	Output
ADDRESS_NUMBER	mcontr_sequencer	Parameter
dly_data	mcontr_sequencer	Signal
dly_addr	mcontr_sequencer	Signal
ld_delay	mcontr_sequencer	Signal
set	mcontr_sequencer	Signal
phy_0bit_addr	mcontr_sequencer	Signal
phy_0bit_we	mcontr_sequencer	Signal
cmda_en	mcontr_sequencer	Signal
ddr_rst	mcontr_sequencer	Signal
dci_rst	mcontr_sequencer	Signal
dly_rst	mcontr_sequencer	Signal
ddr_cke	mcontr_sequencer	Signal
dqs_pattern	mcontr_sequencer	Signal
dqm_pattern	mcontr_sequencer	Signal
dq_tri_on_pattern	mcontr_sequencer	Signal
dq_tri_off_pattern	mcontr_sequencer	Signal
dqs_tri_on_pattern	mcontr_sequencer	Signal
dqs_tri_off_pattern	mcontr_sequencer	Signal
wbuf_delay	mcontr_sequencer	Signal
wbuf_delay_m1	mcontr_sequencer	Signal
phy_16bit_addr	mcontr_sequencer	Signal
phy_16bit_data	mcontr_sequencer	Signal
phy_16bit_we	mcontr_sequencer	Signal
inv_clk_div	mcontr_sequencer	Signal
locked_mmcm	mcontr_sequencer	Signal
locked_pll	mcontr_sequencer	Signal
dly_ready	mcontr_sequencer	Signal
dci_ready	mcontr_sequencer	Signal
ps_out	mcontr_sequencer	Signal
ps_rdy	mcontr_sequencer	Signal
status_data	mcontr_sequencer	Signal
phy_locked_mmcm	mcontr_sequencer	Signal
phy_locked_pll	mcontr_sequencer	Signal
phy_dly_ready	mcontr_sequencer	Signal
phy_dci_ready	mcontr_sequencer	Signal
phy_cmd_word	mcontr_sequencer	Signal
phy_cmd0_word	mcontr_sequencer	Signal
phy_cmd1_word	mcontr_sequencer	Signal
buf_raddr_reset	mcontr_sequencer	Signal
buf_addr_reset	mcontr_sequencer	Signal
buf_waddr_reset_negedge	mcontr_sequencer	Signal
buf_wr_negedge	mcontr_sequencer	Signal
buf_wdata	mcontr_sequencer	Signal
buf_wdata_negedge	mcontr_sequencer	Signal
buf_rdata	mcontr_sequencer	Signal
buf_wr	mcontr_sequencer	Signal
buf_wr_ndly	mcontr_sequencer	Signal
buf_rd	mcontr_sequencer	Signal
buf_rst	mcontr_sequencer	Signal
buf_rst_d	mcontr_sequencer	Signal
cmd_addr	mcontr_sequencer	Signal
cmd_sel	mcontr_sequencer	Signal
cmd_busy	mcontr_sequencer	Signal
phy_cmd_nop	mcontr_sequencer	Signal
phy_cmd_add_pause	mcontr_sequencer	Signal
add_pause	mcontr_sequencer	Signal
sequence_done	mcontr_sequencer	Signal
pause_len	mcontr_sequencer	Signal
cmd_fetch	mcontr_sequencer	Signal
pause	mcontr_sequencer	Signal
pause_cntr	mcontr_sequencer	Signal
run_chn_w_d	mcontr_sequencer	Signal
run_refresh_w_d	mcontr_sequencer	Signal
run_w_d	mcontr_sequencer	Signal
run_chn_d	mcontr_sequencer	Signal
run_refresh_d	mcontr_sequencer	Signal
run_chn_w_d_negedge	mcontr_sequencer	Signal
run_refresh_w_d_negedge	mcontr_sequencer	Signal
run_w_d_negedge	mcontr_sequencer	Signal
run_seq_d	mcontr_sequencer	Signal
mem_read_mode	mcontr_sequencer	Signal
tmp_debug_a	mcontr_sequencer	Signal
set_patterns	mcontr_sequencer	Signal
set_patterns_tri	mcontr_sequencer	Signal
set_wbuf_delay	mcontr_sequencer	Signal
set_extra	mcontr_sequencer	Signal
control_status_we	mcontr_sequencer	Signal
contral_status_data	mcontr_sequencer	Signal
ren0	mcontr_sequencer	Signal
ren1	mcontr_sequencer	Signal
width	scheduler16	Parameter
n_chn	scheduler16	Parameter
mrst	scheduler16	Input
clk	scheduler16	Input
chn_en	scheduler16	Input
want_rq	scheduler16	Input
need_rq	scheduler16	Input
en_schedul	scheduler16	Input
need	scheduler16	Output
grant	scheduler16	Output
grant_chn	scheduler16	Output
pgm_addr	scheduler16	Input
pgm_data	scheduler16	Input
pgm_en	scheduler16	Input
pri_reg	scheduler16	Signal
want_conf	scheduler16	Signal
need_conf	scheduler16	Signal
need_want_conf	scheduler16	Signal
need_want_conf_d	scheduler16	Signal
want_set	scheduler16	Signal
need_set	scheduler16	Signal
want_need_set_r	scheduler16	Signal
need_r	scheduler16	Signal
need_r2	scheduler16	Signal
sched_state	scheduler16	Signal
need_some	scheduler16	Signal
next_want_conf	scheduler16	Signal
next_need_conf	scheduler16	Signal
need_want_conf_w	scheduler16	Signal
index	scheduler16	Signal
index_valid	scheduler16	Signal
grant_r	scheduler16	Signal
grant_sent	scheduler16	Signal
grant_chn_r	scheduler16	Signal
grant_w	scheduler16	Signal
cmd_deser.ADDR	cmd_deser	Parameter
mcontr_sequencer.ADDR	cmd_deser	Parameter
cmd_deser.ADDR_MASK	cmd_deser	Parameter
mcontr_sequencer.ADDR_MASK	cmd_deser	Parameter
cmd_deser.NUM_CYCLES	cmd_deser	Parameter
mcontr_sequencer.NUM_CYCLES	cmd_deser	Parameter
cmd_deser.ADDR_WIDTH	cmd_deser	Parameter
mcontr_sequencer.ADDR_WIDTH	cmd_deser	Parameter
cmd_deser.DATA_WIDTH	cmd_deser	Parameter
mcontr_sequencer.DATA_WIDTH	cmd_deser	Parameter
cmd_deser.ADDR1	cmd_deser	Parameter
mcontr_sequencer.ADDR1	cmd_deser	Parameter
cmd_deser.ADDR_MASK1	cmd_deser	Parameter
mcontr_sequencer.ADDR_MASK1	cmd_deser	Parameter
cmd_deser.ADDR2	cmd_deser	Parameter
mcontr_sequencer.ADDR2	cmd_deser	Parameter
cmd_deser.ADDR_MASK2	cmd_deser	Parameter
mcontr_sequencer.ADDR_MASK2	cmd_deser	Parameter
cmd_deser.WE_EARLY	cmd_deser	Parameter
mcontr_sequencer.WE_EARLY	cmd_deser	Parameter
cmd_deser.rst	cmd_deser	Input
mcontr_sequencer.rst	cmd_deser	Input
cmd_deser.clk	cmd_deser	Input
mcontr_sequencer.clk	cmd_deser	Input
cmd_deser.srst	cmd_deser	Input
mcontr_sequencer.srst	cmd_deser	Input
cmd_deser.ad	cmd_deser	Input
mcontr_sequencer.ad	cmd_deser	Input
cmd_deser.stb	cmd_deser	Input
mcontr_sequencer.stb	cmd_deser	Input
cmd_deser.addr	cmd_deser	Output
mcontr_sequencer.addr	cmd_deser	Output
cmd_deser.data	cmd_deser	Output
mcontr_sequencer.data	cmd_deser	Output
cmd_deser.we	cmd_deser	Output
mcontr_sequencer.we	cmd_deser	Output
cmd_deser.WE_WIDTH	cmd_deser	Parameter
mcontr_sequencer.WE_WIDTH	cmd_deser	Parameter
ALWAYS_271 clk	ddr_refresh	Always Construct
ALWAYS_295 mclk	memctrl16	Always Construct
ALWAYS_296 mclk	memctrl16	Always Construct
ALWAYS_297 mclk	memctrl16	Always Construct
ALWAYS_298 mclk	memctrl16	Always Construct
ALWAYS_299 mclk	memctrl16	Always Construct
ALWAYS_300 mclk	memctrl16	Always Construct
ALWAYS_301 mclk	memctrl16	Always Construct
ALWAYS_302 mclk	memctrl16	Always Construct
ALWAYS_303 mclk	memctrl16	Always Construct
ALWAYS_304 mclk	memctrl16	Always Construct
ALWAYS_305 mclk	memctrl16	Always Construct
ALWAYS_306 mclk	memctrl16	Always Construct
ALWAYS_307 mclk	memctrl16	Always Construct
ALWAYS_308 mclk	memctrl16	Always Construct
ALWAYS_309 mclk	memctrl16	Always Construct
ALWAYS_310 mclk	memctrl16	Always Construct
ALWAYS_311 mclk	memctrl16	Always Construct
ALWAYS_312 mclk	memctrl16	Always Construct
ALWAYS_313 mclk	memctrl16	Always Construct
ALWAYS_316 mclk	mcontr_sequencer	Always Construct
ALWAYS_317 mclk	mcontr_sequencer	Always Construct
ALWAYS_318 mclk	mcontr_sequencer	Always Construct
ALWAYS_319 mclk	mcontr_sequencer	Always Construct
ALWAYS_320 mclk	mcontr_sequencer	Always Construct
ALWAYS_331 clk	scheduler16	Always Construct
ALWAYS_332 clk	scheduler16	Always Construct
ALWAYS_333 clk	scheduler16	Always Construct
ALWAYS_498 clk	dly01_16	Always Construct
ALWAYS_521 clk	mcont_common_chnbuf_reg	Always Construct
ALWAYS_522 clk	mcont_common_chnbuf_reg	Always Construct
ALWAYS_523 clk	mcont_from_chnbuf_reg	Always Construct
ALWAYS_524 clk	mcont_from_chnbuf_reg	Always Construct
ALWAYS_525 clk	mcont_from_chnbuf_reg	Always Construct
ALWAYS_526 clk	mcont_from_chnbuf_reg	Always Construct
ALWAYS_527 clk	mcont_to_chnbuf_reg	Always Construct
ALWAYS_528 clk	mcont_to_chnbuf_reg	Always Construct
ALWAYS_529 clk	mcont_to_chnbuf_reg	Always Construct
ALWAYS_530 clk	mcont_to_chnbuf_reg	Always Construct
ALWAYS_546 rst or clk	status_router2	Always Construct
cmd_deser	memctrl16
cmd_deser	memctrl16
cmd_deser	memctrl16
cmd_deser.cmd_deser_dual	cmd_deser	Module Instance
mcontr_sequencer.cmd_deser_dual	cmd_deser	Module Instance
cmd_deser.cmd_deser_multi	cmd_deser	Module Instance
mcontr_sequencer.cmd_deser_multi	cmd_deser	Module Instance
cmd_deser.cmd_deser_single	cmd_deser	Module Instance
mcontr_sequencer.cmd_deser_single	cmd_deser	Module Instance
ddr_refresh	memctrl16
dly01_16	dly_16	Module Instance
dly_16	memctrl16
fifo_1cycle	status_router2	Module Instance
fifo_1cycle	status_router2	Module Instance
fifo_same_clock	status_router2	Module Instance
fifo_same_clock	status_router2	Module Instance
status_router2.GENERATE [122]	status_router2	GENERATE
scheduler16.GENERATE [122]	scheduler16	GENERATE
GENERATE [50]	dly_16	GENERATE
cmd_deser.GENERATE [63]	cmd_deser	GENERATE
mcontr_sequencer.GENERATE [63]	cmd_deser	GENERATE
status_generate.GENERATE [68]	status_generate	GENERATE
mcontr_sequencer.GENERATE [68]	status_generate	GENERATE
GENERATE [78]	scheduler16	GENERATE
index_max_16	scheduler16	Module Instance
mcont_common_chnbuf_reg	memctrl16
mcont_common_chnbuf_reg	memctrl16
mcont_common_chnbuf_reg	memctrl16
mcont_common_chnbuf_reg	memctrl16
mcont_common_chnbuf_reg	memctrl16
mcont_common_chnbuf_reg	memctrl16
mcont_common_chnbuf_reg	memctrl16
mcont_common_chnbuf_reg	memctrl16
mcont_common_chnbuf_reg	memctrl16
mcont_common_chnbuf_reg	memctrl16
mcont_common_chnbuf_reg	memctrl16
mcont_common_chnbuf_reg	memctrl16
mcont_common_chnbuf_reg	memctrl16
mcont_from_chnbuf_reg	memctrl16
mcont_from_chnbuf_reg	memctrl16
mcont_from_chnbuf_reg	memctrl16
mcont_from_chnbuf_reg	memctrl16
mcont_from_chnbuf_reg	memctrl16
mcont_from_chnbuf_reg	memctrl16
mcont_from_chnbuf_reg	memctrl16
mcont_from_chnbuf_reg	memctrl16
mcont_from_chnbuf_reg	memctrl16
mcont_to_chnbuf_reg	memctrl16
mcont_to_chnbuf_reg	memctrl16
mcont_to_chnbuf_reg	memctrl16
mcont_to_chnbuf_reg	memctrl16
mcont_to_chnbuf_reg	memctrl16
mcont_to_chnbuf_reg	memctrl16
mcont_to_chnbuf_reg	memctrl16
mcont_to_chnbuf_reg	memctrl16
mcont_to_chnbuf_reg	memctrl16
mcontr_sequencer	memctrl16
phy_cmd	mcontr_sequencer	Module Instance
pri1hot16	scheduler16	Module Instance
pri1hot16	scheduler16	Module Instance
ram_1kx32_1kx32	mcontr_sequencer	Module Instance
ram_1kx32_1kx32	mcontr_sequencer	Module Instance
scheduler16	memctrl16
status_generate	memctrl16
status_generate.status_generate_extra	status_generate	Module Instance
mcontr_sequencer.status_generate_extra	status_generate	Module Instance
status_generate.status_generate_only	status_generate	Module Instance
mcontr_sequencer.status_generate_only	status_generate	Module Instance
status_router2	memctrl16