huffman_snglclk Member List

This is the complete list of members for huffman_snglclk, including all inherited members.

WIDTH	dly_16	Parameter
clk	dly_16	Input
rst	dly_16	Input
dly	dly_16	Input
din	dly_16	Input
dout	dly_16	Output
DATA_WIDTH	fifo_same_clock	Parameter
DATA_DEPTH	fifo_same_clock	Parameter
rst	fifo_same_clock	Input
clk	fifo_same_clock	Input
sync_rst	fifo_same_clock	Input
we	fifo_same_clock	Input
re	fifo_same_clock	Input
data_in	fifo_same_clock	Input
data_out	fifo_same_clock	Output
nempty	fifo_same_clock	Output
half_full	fifo_same_clock	Output
DATA_2DEPTH	fifo_same_clock	Parameter
fill	fifo_same_clock	Signal
inreg	fifo_same_clock	Signal
outreg	fifo_same_clock	Signal
ra	fifo_same_clock	Signal
wa	fifo_same_clock	Signal
wem	fifo_same_clock	Signal
rem	fifo_same_clock	Signal
out_full	fifo_same_clock	Signal
ram	fifo_same_clock	Signal
ram_nempty	fifo_same_clock	Signal
EXTRA_DLY	pulse_cross_clock	Parameter
rst	pulse_cross_clock	Input
src_clk	pulse_cross_clock	Input
dst_clk	pulse_cross_clock	Input
in_pulse	pulse_cross_clock	Input
out_pulse	pulse_cross_clock	Output
busy	pulse_cross_clock	Output
EXTRA_DLY_SAFE	pulse_cross_clock	Parameter
in_reg	pulse_cross_clock	Signal
out_reg	pulse_cross_clock	Signal
busy_r	pulse_cross_clock	Signal
MODE_16_BITS	table_ad_receive	Parameter
NUM_CHN	table_ad_receive	Parameter
clk	table_ad_receive	Input
a_not_d	table_ad_receive	Input
ser_d	table_ad_receive	Input
dv	table_ad_receive	Input
ta	table_ad_receive	Output
td	table_ad_receive	Output
twe	table_ad_receive	Output
addr_r	table_ad_receive	Signal
twe_r	table_ad_receive	Signal
td_r	table_ad_receive	Signal
REGISTERS	ram18_var_w_var_r	Parameter
LOG2WIDTH_WR	ram18_var_w_var_r	Parameter
LOG2WIDTH_RD	ram18_var_w_var_r	Parameter
11587	ram18_var_w_var_r	Parameter
rclk	ram18_var_w_var_r	Input
raddr	ram18_var_w_var_r	Input
ren	ram18_var_w_var_r	Input
regen	ram18_var_w_var_r	Input
data_out	ram18_var_w_var_r	Output
wclk	ram18_var_w_var_r	Input
waddr	ram18_var_w_var_r	Input
we	ram18_var_w_var_r	Input
web	ram18_var_w_var_r	Input
data_in	ram18_var_w_var_r	Input
clk	huffman_merge_code_literal	Input
in_valid	huffman_merge_code_literal	Input
huff_code	huffman_merge_code_literal	Input
huff_code_len	huffman_merge_code_literal	Input
literal	huffman_merge_code_literal	Input
literal_len	huffman_merge_code_literal	Input
out_valid	huffman_merge_code_literal	Output
out_bits	huffman_merge_code_literal	Output
out_len	huffman_merge_code_literal	Output
lit0	huffman_merge_code_literal	Signal
lit1	huffman_merge_code_literal	Signal
lit2	huffman_merge_code_literal	Signal
huff0	huffman_merge_code_literal	Signal
huff1	huffman_merge_code_literal	Signal
huff2	huffman_merge_code_literal	Signal
data3	huffman_merge_code_literal	Signal
llen0	huffman_merge_code_literal	Signal
llen1	huffman_merge_code_literal	Signal
llen2	huffman_merge_code_literal	Signal
olen3	huffman_merge_code_literal	Signal
hlen0	huffman_merge_code_literal	Signal
hlen1	huffman_merge_code_literal	Signal
hlen2	huffman_merge_code_literal	Signal
hlen2m1	huffman_merge_code_literal	Signal
hlen3m1	huffman_merge_code_literal	Signal
valid	huffman_merge_code_literal	Signal
xclk	huffman_snglclk
rst	huffman_snglclk
mclk	huffman_snglclk
tser_we	huffman_snglclk
tser_a_not_d	huffman_snglclk
tser_d	huffman_snglclk
di	huffman_snglclk
ds	huffman_snglclk
do27	huffman_snglclk
dl	huffman_snglclk
dv	huffman_snglclk
flush	huffman_snglclk
last_block	huffman_snglclk
test_lbw	huffman_snglclk
gotLastBlock	huffman_snglclk
clk_flush	huffman_snglclk
flush_clk	huffman_snglclk
fifo_or_full	huffman_snglclk
fifo_re_r	huffman_snglclk
fifo_rdy	huffman_snglclk
fifo_re	huffman_snglclk
fifo_out	huffman_snglclk
gotDC	huffman_snglclk
gotAC	huffman_snglclk
gotRLL	huffman_snglclk
gotEOB	huffman_snglclk
gotLastWord	huffman_snglclk
gotColor	huffman_snglclk
rll	huffman_snglclk
rll_late	huffman_snglclk
gotAC_r	huffman_snglclk
gotDC_r	huffman_snglclk
gotEOB_r	huffman_snglclk
gotColor_r	huffman_snglclk
gotF0_r	huffman_snglclk
sval	huffman_snglclk
val_length	huffman_snglclk
val_literal	huffman_snglclk
htable_addr	huffman_snglclk
htable_re	huffman_snglclk
htable_out	huffman_snglclk
val_length_late	huffman_snglclk
val_literal_late	huffman_snglclk
ready_to_flush	huffman_snglclk
flush_r	huffman_snglclk
last_block_r	huffman_snglclk
active_r	huffman_snglclk
active	huffman_snglclk
twe	huffman_snglclk
tdi	huffman_snglclk
ta	huffman_snglclk
clk	varlen_encode_snglclk	Input
d	varlen_encode_snglclk	Input
l	varlen_encode_snglclk	Output
q	varlen_encode_snglclk	Output
d1	varlen_encode_snglclk	Signal
this0	varlen_encode_snglclk	Signal
this1	varlen_encode_snglclk	Signal
this2	varlen_encode_snglclk	Signal
codel0	varlen_encode_snglclk	Signal
codel1	varlen_encode_snglclk	Signal
codel2	varlen_encode_snglclk	Signal
codel	varlen_encode_snglclk	Signal
ALWAYS_163 clk	huffman_merge_code_literal	Always Construct
ALWAYS_164 xclk	huffman_snglclk	Always Construct
ALWAYS_196 clk	varlen_encode_snglclk	Always Construct
ALWAYS_508 clk or rst	fifo_same_clock	Always Construct
ALWAYS_509 clk	fifo_same_clock	Always Construct
ALWAYS_532 src_clk or rst	pulse_cross_clock	Always Construct
ALWAYS_533 dst_clk	pulse_cross_clock	Always Construct
ALWAYS_549 clk	table_ad_receive	Always Construct
dly01_16	dly_16	Module Instance
dly_16	huffman_snglclk
dly_16	huffman_snglclk
dly_16	huffman_snglclk
fifo_same_clock	huffman_snglclk
GENERATE [123]	ram18_var_w_var_r	GENERATE
GENERATE [50]	dly_16	GENERATE
GENERATE [68]	table_ad_receive	GENERATE
huffman.dat.vh	huffman_snglclk
huffman_merge_code_literal	huffman_snglclk
pulse_cross_clock	huffman_snglclk
ram18_32w_32r	ram18_var_w_var_r	Module Instance
ram18_32w_lt32r	ram18_var_w_var_r	Module Instance
ram18_declare_init.vh	ram18_var_w_var_r	Include
ram18_dummy	ram18_var_w_var_r	Module Instance
ram18_lt32w_32r	ram18_var_w_var_r	Module Instance
ram18_lt32w_lt32r	ram18_var_w_var_r	Module Instance
ram18_pass_init.vh	ram18_var_w_var_r	Include
ram18_var_w_var_r	huffman_snglclk
table_ad_receive	huffman_snglclk
varlen_encode_snglclk	huffman_snglclk