Static Public Member Functions

Always Constructs
ALWAYS_11	( mclk )
ALWAYS_12	( aclk )
ALWAYS_13	( mclk )
ALWAYS_14	( mclk )
ALWAYS_15	( mclk )
ALWAYS_16	( aclk )

Public Attributes

Inputs
mclk
aclk
mrst
arst
frame0	[NUM_FRAME_BITS- 1 : 0 ]
hist_request0
hist_chn0	[ 1 : 0 ]
hist_dvalid0
hist_data0	[ 31 : 0 ]
frame1	[NUM_FRAME_BITS- 1 : 0 ]
hist_request1
hist_chn1	[ 1 : 0 ]
hist_dvalid1
hist_data1	[ 31 : 0 ]
frame2	[NUM_FRAME_BITS- 1 : 0 ]
hist_request2
hist_chn2	[ 1 : 0 ]
hist_dvalid2
hist_data2	[ 31 : 0 ]
frame3	[NUM_FRAME_BITS- 1 : 0 ]
hist_request3
hist_chn3	[ 1 : 0 ]
hist_dvalid3
hist_data3	[ 31 : 0 ]
cmd_ad	[ 7 : 0 ]
cmd_stb
saxi_awready
saxi_wready
saxi_bvalid
saxi_bid	[ 5 : 0 ]
saxi_bresp	[ 1 : 0 ]
debug_sl
debug_di

Outputs
hist_grant0
hist_grant1
hist_grant2
hist_grant3
saxi_awaddr	[ 31 : 0 ]
saxi_awvalid
saxi_awid	[ 5 : 0 ]
saxi_awlock	[ 1 : 0 ]
saxi_awcache	[ 3 : 0 ]
saxi_awprot	[ 2 : 0 ]
saxi_awlen	[ 3 : 0 ]
saxi_awsize	[ 1 : 0 ]
saxi_awburst	[ 1 : 0 ]
saxi_awqos	[ 3 : 0 ]
saxi_wdata	[ 31 : 0 ]
saxi_wvalid
saxi_wid	[ 5 : 0 ]
saxi_wlast
saxi_wstrb	[ 3 : 0 ]
saxi_bready
debug_do

Parameters
HIST_SAXI_ADDR	'h380
HIST_SAXI_ADDR_MASK	'h7f0
HIST_SAXI_MODE_ADDR	'h390
HIST_SAXI_MODE_WIDTH	8
HIST_SAXI_EN	0
HIST_SAXI_NRESET	1
HIST_CONFIRM_WRITE	2
HIST_SAXI_AWCACHE	4
HIST_SAXI_MODE_ADDR_MASK	'h7ff
377
378
ATTRIB_WIDTH	NUM_FRAME_BITS + 4 + 2

Signals
reg[HIST_SAXI_MODE_WIDTH - 1 : 0 ]	mode
wire	en
reg[ 3 : 0 ]	awcache_mode
reg	confirm_write
wire	nreset
wire	we_mode
wire	we_addr
wire[ 31 : 0 ]	cmd_data
wire[ 3 : 0 ]	cmd_wa
reg[ 19 : 0 ]	hist_start_page [ 0 : 15 ]
reg[ 2 : 0 ]	burst
wire[ 3 : 0 ]	pri_rq
reg[ 2 : 0 ]	enc_rq
wire	busy_w
reg	busy_r
reg[ 1 : 0 ]	mux_sel
wire	start_w
reg	started
reg[ 4 ATTRIB_WIDTH* - 1 : 0 ]**	attrib
wire	page_sent_mclk
reg[ 1 : 0 ]	page_wr
reg[ 7 : 0 ]	page_wa
reg[ 2 : 0 ]	pages_in_buf_wr
wire	buf_full
wire	dav
reg	dav_r
wire	burst_done_w
reg	grant
wire[ 31 : 0 ]	din
reg[ 31 : 0 ]	din_r
wire	rq_in
wire[ 1 : 0 ]	sub_chn_w
reg[ 1 : 0 ]	sub_chn_r
wire[NUM_FRAME_BITS- 1 : 0 ]	frame_w
reg[NUM_FRAME_BITS- 1 : 0 ]	frame_r
reg	wr_attr
wire[ 3 : 0 ]	chn_sel
reg[ 3 : 0 ]	chn_grant
wire	page_sent_aclk
reg	preen_aclk
reg	en_aclk
reg	prenreset_aclk
reg	nreset_aclk
wire	page_written_aclk
reg[ 2 : 0 ]	pages_in_buf_rd
reg[ 1 : 0 ]	page_rd
reg[ 7 : 0 ]	page_ra
wire	buf_empty
reg[ 3 : 0 ]	block_run
wire	block_start_w
reg[ 3 : 0 ]	block_start_r
wire	block_end
reg[NUM_FRAME_BITS+ 4 + 2 - 1 : 0 ]	attrib_r
wire[ 3 : 0 ]	attrib_chn
wire[NUM_FRAME_BITS- 1 : 0 ]	attrib_frame
wire[ 1 : 0 ]	attrib_color
reg[ 19 : 0 ]	hist_start_page_r
reg[ 31 : 10 ]	hist_start_addr
reg[ 31 : 6 ]	start_addr_r
wire	saxi_start_burst_w
reg	first_burst
wire[ 31 : 0 ]	inter_buf_data
reg[ 3 : 0 ]	wburst_cntr
reg[ 4 : 0 ]	num_bursts_in_buf
reg[ 4 : 0 ]	num_bursts_pending
wire	fifo_nempty
wire	fifo_half_full
reg[ 2 : 0 ]	buf_re
wire	buf_re_w
wire	fifo_re
reg	saxi_bvalid_r
reg	page_read_run
reg[ 7 : 0 ]	extra_wa
reg[ 7 : 0 ]	extra_ra
reg[ 15 : 0 ]	num_addr_saxi
reg[ 15 : 0 ]	num_data_saxi

Module Instances
debug_slave::debug_slave_i	Module debug_slave
pulse_cross_clock::pulse_cross_clock_page_sent_i	Module pulse_cross_clock
pulse_cross_clock::pulse_cross_clock_page_written_aclk_i	Module pulse_cross_clock
cmd_deser::cmd_deser_histogram_saxi_i	Module cmd_deser
ram_var_w_var_r::ram_var_w_var_r_i	Module ram_var_w_var_r
fifo_same_clock::fifo_same_clock_i	Module fifo_same_clock