x393
1.0
FPGAcodeforElphelNC393camera
histogram_saxi Member List
This is the complete list of members for
histogram_saxi
, including all inherited members.
SHIFT_WIDTH
debug_slave
Parameter
READ_WIDTH
debug_slave
Parameter
WRITE_WIDTH
debug_slave
Parameter
DEBUG_CMD_LATENCY
debug_slave
Parameter
mclk
debug_slave
Input
mrst
debug_slave
Input
debug_di
debug_slave
Input
debug_sl
debug_slave
Input
debug_do
debug_slave
Output
rd_data
debug_slave
Input
wr_data
debug_slave
Output
stb
debug_slave
Output
data_sr
debug_slave
Signal
cmd
debug_slave
Signal
cmd_reg
debug_slave
Signal
cmd_reg_dly
debug_slave
Signal
ext_rdata
debug_slave
Signal
DATA_WIDTH
fifo_same_clock
Parameter
DATA_DEPTH
fifo_same_clock
Parameter
rst
fifo_same_clock
Input
clk
fifo_same_clock
Input
sync_rst
fifo_same_clock
Input
we
fifo_same_clock
Input
re
fifo_same_clock
Input
data_in
fifo_same_clock
Input
data_out
fifo_same_clock
Output
nempty
fifo_same_clock
Output
half_full
fifo_same_clock
Output
DATA_2DEPTH
fifo_same_clock
Parameter
fill
fifo_same_clock
Signal
inreg
fifo_same_clock
Signal
outreg
fifo_same_clock
Signal
ra
fifo_same_clock
Signal
wa
fifo_same_clock
Signal
wem
fifo_same_clock
Signal
rem
fifo_same_clock
Signal
out_full
fifo_same_clock
Signal
ram
fifo_same_clock
Signal
ram_nempty
fifo_same_clock
Signal
EXTRA_DLY
pulse_cross_clock
Parameter
rst
pulse_cross_clock
Input
src_clk
pulse_cross_clock
Input
dst_clk
pulse_cross_clock
Input
in_pulse
pulse_cross_clock
Input
out_pulse
pulse_cross_clock
Output
busy
pulse_cross_clock
Output
EXTRA_DLY_SAFE
pulse_cross_clock
Parameter
in_reg
pulse_cross_clock
Signal
out_reg
pulse_cross_clock
Signal
busy_r
pulse_cross_clock
Signal
REGISTERS
ram_var_w_var_r
Parameter
LOG2WIDTH_WR
ram_var_w_var_r
Parameter
LOG2WIDTH_RD
ram_var_w_var_r
Parameter
11862
ram_var_w_var_r
Parameter
rclk
ram_var_w_var_r
Input
raddr
ram_var_w_var_r
Input
ren
ram_var_w_var_r
Input
regen
ram_var_w_var_r
Input
data_out
ram_var_w_var_r
Output
wclk
ram_var_w_var_r
Input
waddr
ram_var_w_var_r
Input
we
ram_var_w_var_r
Input
web
ram_var_w_var_r
Input
data_in
ram_var_w_var_r
Input
HIST_SAXI_ADDR
histogram_saxi
HIST_SAXI_ADDR_MASK
histogram_saxi
HIST_SAXI_MODE_ADDR
histogram_saxi
HIST_SAXI_MODE_WIDTH
histogram_saxi
HIST_SAXI_EN
histogram_saxi
HIST_SAXI_NRESET
histogram_saxi
HIST_CONFIRM_WRITE
histogram_saxi
HIST_SAXI_AWCACHE
histogram_saxi
HIST_SAXI_MODE_ADDR_MASK
histogram_saxi
377
histogram_saxi
378
histogram_saxi
mclk
histogram_saxi
aclk
histogram_saxi
mrst
histogram_saxi
arst
histogram_saxi
frame0
histogram_saxi
hist_request0
histogram_saxi
hist_grant0
histogram_saxi
hist_chn0
histogram_saxi
hist_dvalid0
histogram_saxi
hist_data0
histogram_saxi
frame1
histogram_saxi
hist_request1
histogram_saxi
hist_grant1
histogram_saxi
hist_chn1
histogram_saxi
hist_dvalid1
histogram_saxi
hist_data1
histogram_saxi
frame2
histogram_saxi
hist_request2
histogram_saxi
hist_grant2
histogram_saxi
hist_chn2
histogram_saxi
hist_dvalid2
histogram_saxi
hist_data2
histogram_saxi
frame3
histogram_saxi
hist_request3
histogram_saxi
hist_grant3
histogram_saxi
hist_chn3
histogram_saxi
hist_dvalid3
histogram_saxi
hist_data3
histogram_saxi
cmd_ad
histogram_saxi
cmd_stb
histogram_saxi
saxi_awaddr
histogram_saxi
saxi_awvalid
histogram_saxi
saxi_awready
histogram_saxi
saxi_awid
histogram_saxi
saxi_awlock
histogram_saxi
saxi_awcache
histogram_saxi
saxi_awprot
histogram_saxi
saxi_awlen
histogram_saxi
saxi_awsize
histogram_saxi
saxi_awburst
histogram_saxi
saxi_awqos
histogram_saxi
saxi_wdata
histogram_saxi
saxi_wvalid
histogram_saxi
saxi_wready
histogram_saxi
saxi_wid
histogram_saxi
saxi_wlast
histogram_saxi
saxi_wstrb
histogram_saxi
saxi_bvalid
histogram_saxi
saxi_bready
histogram_saxi
saxi_bid
histogram_saxi
saxi_bresp
histogram_saxi
debug_do
histogram_saxi
debug_sl
histogram_saxi
debug_di
histogram_saxi
ATTRIB_WIDTH
histogram_saxi
mode
histogram_saxi
en
histogram_saxi
awcache_mode
histogram_saxi
confirm_write
histogram_saxi
nreset
histogram_saxi
we_mode
histogram_saxi
we_addr
histogram_saxi
cmd_data
histogram_saxi
cmd_wa
histogram_saxi
hist_start_page
histogram_saxi
burst
histogram_saxi
pri_rq
histogram_saxi
enc_rq
histogram_saxi
busy_w
histogram_saxi
busy_r
histogram_saxi
mux_sel
histogram_saxi
start_w
histogram_saxi
started
histogram_saxi
attrib
histogram_saxi
page_sent_mclk
histogram_saxi
page_wr
histogram_saxi
page_wa
histogram_saxi
pages_in_buf_wr
histogram_saxi
buf_full
histogram_saxi
dav
histogram_saxi
dav_r
histogram_saxi
burst_done_w
histogram_saxi
grant
histogram_saxi
din
histogram_saxi
din_r
histogram_saxi
rq_in
histogram_saxi
sub_chn_w
histogram_saxi
sub_chn_r
histogram_saxi
frame_w
histogram_saxi
frame_r
histogram_saxi
wr_attr
histogram_saxi
chn_sel
histogram_saxi
chn_grant
histogram_saxi
page_sent_aclk
histogram_saxi
preen_aclk
histogram_saxi
en_aclk
histogram_saxi
prenreset_aclk
histogram_saxi
nreset_aclk
histogram_saxi
page_written_aclk
histogram_saxi
pages_in_buf_rd
histogram_saxi
page_rd
histogram_saxi
page_ra
histogram_saxi
buf_empty
histogram_saxi
block_run
histogram_saxi
block_start_w
histogram_saxi
block_start_r
histogram_saxi
block_end
histogram_saxi
attrib_r
histogram_saxi
attrib_chn
histogram_saxi
attrib_frame
histogram_saxi
attrib_color
histogram_saxi
hist_start_page_r
histogram_saxi
hist_start_addr
histogram_saxi
start_addr_r
histogram_saxi
saxi_start_burst_w
histogram_saxi
first_burst
histogram_saxi
inter_buf_data
histogram_saxi
wburst_cntr
histogram_saxi
num_bursts_in_buf
histogram_saxi
num_bursts_pending
histogram_saxi
fifo_nempty
histogram_saxi
fifo_half_full
histogram_saxi
buf_re
histogram_saxi
buf_re_w
histogram_saxi
fifo_re
histogram_saxi
saxi_bvalid_r
histogram_saxi
page_read_run
histogram_saxi
extra_wa
histogram_saxi
extra_ra
histogram_saxi
num_addr_saxi
histogram_saxi
num_data_saxi
histogram_saxi
ADDR
cmd_deser
Parameter
ADDR_MASK
cmd_deser
Parameter
NUM_CYCLES
cmd_deser
Parameter
ADDR_WIDTH
cmd_deser
Parameter
DATA_WIDTH
cmd_deser
Parameter
ADDR1
cmd_deser
Parameter
ADDR_MASK1
cmd_deser
Parameter
ADDR2
cmd_deser
Parameter
ADDR_MASK2
cmd_deser
Parameter
WE_EARLY
cmd_deser
Parameter
rst
cmd_deser
Input
clk
cmd_deser
Input
srst
cmd_deser
Input
ad
cmd_deser
Input
stb
cmd_deser
Input
addr
cmd_deser
Output
data
cmd_deser
Output
we
cmd_deser
Output
WE_WIDTH
cmd_deser
Parameter
ALWAYS_11
mclk
histogram_saxi
Always Construct
ALWAYS_12
aclk
histogram_saxi
Always Construct
ALWAYS_13
mclk
histogram_saxi
Always Construct
ALWAYS_14
mclk
histogram_saxi
Always Construct
ALWAYS_15
mclk
histogram_saxi
Always Construct
ALWAYS_16
aclk
histogram_saxi
Always Construct
ALWAYS_497
mclk
debug_slave
Always Construct
ALWAYS_508
clk or rst
fifo_same_clock
Always Construct
ALWAYS_509
clk
fifo_same_clock
Always Construct
ALWAYS_532
src_clk or rst
pulse_cross_clock
Always Construct
ALWAYS_533
dst_clk
pulse_cross_clock
Always Construct
cmd_deser
histogram_saxi
cmd_deser_dual
cmd_deser
Module Instance
cmd_deser_multi
cmd_deser
Module Instance
cmd_deser_single
cmd_deser
Module Instance
debug_slave
histogram_saxi
fifo_same_clock
histogram_saxi
GENERATE [107]
ram_var_w_var_r
GENERATE
GENERATE [63]
cmd_deser
GENERATE
pulse_cross_clock
histogram_saxi
pulse_cross_clock
histogram_saxi
ram36_declare_init.vh
ram_var_w_var_r
Include
ram36_pass_init.vh
ram_var_w_var_r
Include
ram_64w_64r
ram_var_w_var_r
Module Instance
ram_64w_lt64r
ram_var_w_var_r
Module Instance
ram_dummy
ram_var_w_var_r
Module Instance
ram_lt64w_64r
ram_var_w_var_r
Module Instance
ram_lt64w_lt64r
ram_var_w_var_r
Module Instance
ram_var_w_var_r
histogram_saxi
Generated by
1.8.12