ahci_top Member List

This is the complete list of members for ahci_top, including all inherited members.

ahci_dma.EXTRA_DLY	pulse_cross_clock	Parameter
ahci_dma.pulse_cross_clock.EXTRA_DLY	pulse_cross_clock	Parameter
ahci_dma.rst	pulse_cross_clock	Input
ahci_dma.pulse_cross_clock.rst	pulse_cross_clock	Input
ahci_dma.src_clk	pulse_cross_clock	Input
ahci_dma.pulse_cross_clock.src_clk	pulse_cross_clock	Input
ahci_dma.dst_clk	pulse_cross_clock	Input
ahci_dma.pulse_cross_clock.dst_clk	pulse_cross_clock	Input
ahci_dma.in_pulse	pulse_cross_clock	Input
ahci_dma.pulse_cross_clock.in_pulse	pulse_cross_clock	Input
ahci_dma.out_pulse	pulse_cross_clock	Output
ahci_dma.pulse_cross_clock.out_pulse	pulse_cross_clock	Output
ahci_dma.busy	pulse_cross_clock	Output
ahci_dma.pulse_cross_clock.busy	pulse_cross_clock	Output
ahci_dma.EXTRA_DLY_SAFE	pulse_cross_clock	Parameter
ahci_dma.pulse_cross_clock.EXTRA_DLY_SAFE	pulse_cross_clock	Parameter
ahci_dma.in_reg	pulse_cross_clock	Signal
ahci_dma.pulse_cross_clock.in_reg	pulse_cross_clock	Signal
ahci_dma.out_reg	pulse_cross_clock	Signal
ahci_dma.pulse_cross_clock.out_reg	pulse_cross_clock	Signal
ahci_dma.busy_r	pulse_cross_clock	Signal
ahci_dma.pulse_cross_clock.busy_r	pulse_cross_clock	Signal
ADDRESS_BITS	ahci_ctrl_stat	Parameter
mrst	ahci_ctrl_stat	Input
mclk	ahci_ctrl_stat	Input
was_hba_rst	ahci_ctrl_stat	Input
was_port_rst	ahci_ctrl_stat	Input
soft_write_addr	ahci_ctrl_stat	Input
soft_write_data	ahci_ctrl_stat	Input
soft_write_en	ahci_ctrl_stat	Input
regs_addr	ahci_ctrl_stat	Output
regs_we	ahci_ctrl_stat	Output
regs_din	ahci_ctrl_stat	Output
update_pending	ahci_ctrl_stat	Output
update_all	ahci_ctrl_stat	Input
update_busy	ahci_ctrl_stat	Output
update_gis	ahci_ctrl_stat	Input
update_pis	ahci_ctrl_stat	Input
update_ssts	ahci_ctrl_stat	Input
update_serr	ahci_ctrl_stat	Input
update_pcmd	ahci_ctrl_stat	Input
update_pci	ahci_ctrl_stat	Input
update_ghc	ahci_ctrl_stat	Input
pcmd_esp	ahci_ctrl_stat	Input
pcmd_cr	ahci_ctrl_stat	Output
pcmd_cr_set	ahci_ctrl_stat	Input
pcmd_cr_reset	ahci_ctrl_stat	Input
pcmd_fr	ahci_ctrl_stat	Input
pcmd_fre	ahci_ctrl_stat	Output
pcmd_clear_bsy_drq	ahci_ctrl_stat	Input
pcmd_clo	ahci_ctrl_stat	Output
pcmd_clear_st	ahci_ctrl_stat	Input
pcmd_st	ahci_ctrl_stat	Output
pfsm_started	ahci_ctrl_stat	Input
pcmd_st_cleared	ahci_ctrl_stat	Output
sirq_TFE	ahci_ctrl_stat	Input
sirq_IF	ahci_ctrl_stat	Input
sirq_INF	ahci_ctrl_stat	Input
sirq_OF	ahci_ctrl_stat	Input
sirq_PRC	ahci_ctrl_stat	Input
sirq_PC	ahci_ctrl_stat	Input
sirq_DP	ahci_ctrl_stat	Input
sirq_UF	ahci_ctrl_stat	Input
sirq_SDB	ahci_ctrl_stat	Input
sirq_DS	ahci_ctrl_stat	Input
sirq_PS	ahci_ctrl_stat	Input
sirq_DHR	ahci_ctrl_stat	Input
serr_DT	ahci_ctrl_stat	Input
serr_DS	ahci_ctrl_stat	Input
serr_DH	ahci_ctrl_stat	Input
serr_DC	ahci_ctrl_stat	Input
serr_DB	ahci_ctrl_stat	Input
serr_DW	ahci_ctrl_stat	Input
serr_DI	ahci_ctrl_stat	Input
serr_EE	ahci_ctrl_stat	Input
serr_EP	ahci_ctrl_stat	Input
serr_EC	ahci_ctrl_stat	Input
serr_ET	ahci_ctrl_stat	Input
serr_EM	ahci_ctrl_stat	Input
serr_EI	ahci_ctrl_stat	Input
serr_diag_X	ahci_ctrl_stat	Output
ssts_ipm_dnp	ahci_ctrl_stat	Input
ssts_ipm_active	ahci_ctrl_stat	Input
ssts_ipm_part	ahci_ctrl_stat	Input
ssts_ipm_slumb	ahci_ctrl_stat	Input
ssts_ipm_devsleep	ahci_ctrl_stat	Input
ssts_spd_dnp	ahci_ctrl_stat	Input
ssts_spd_gen1	ahci_ctrl_stat	Input
ssts_spd_gen2	ahci_ctrl_stat	Input
ssts_spd_gen3	ahci_ctrl_stat	Input
ssts_det_ndnp	ahci_ctrl_stat	Input
ssts_det_dnp	ahci_ctrl_stat	Input
ssts_det_dp	ahci_ctrl_stat	Input
ssts_det_offline	ahci_ctrl_stat	Input
ssts_det	ahci_ctrl_stat	Output
sctl_ipm	ahci_ctrl_stat	Output
sctl_spd	ahci_ctrl_stat	Output
sctl_det	ahci_ctrl_stat	Output
sctl_det_changed	ahci_ctrl_stat	Output
sctl_det_reset	ahci_ctrl_stat	Input
pxci0_clear	ahci_ctrl_stat	Input
pxci0	ahci_ctrl_stat	Output
hba_reset_done	ahci_ctrl_stat	Input
unsolicited_en	ahci_ctrl_stat	Output
irq	ahci_ctrl_stat	Output
swr_GHC__IS	ahci_ctrl_stat	Signal
swr_HBA_PORT__PxCMD	ahci_ctrl_stat	Signal
swr_HBA_PORT__PxIS	ahci_ctrl_stat	Signal
swr_HBA_PORT__PxIE	ahci_ctrl_stat	Signal
swr_HBA_PORT__PxSCTL	ahci_ctrl_stat	Signal
swr_HBA_PORT__PxSERR	ahci_ctrl_stat	Signal
swr_HBA_PORT__PxCI	ahci_ctrl_stat	Signal
swr_GHC__GHC	ahci_ctrl_stat	Signal
hba_rst_r	ahci_ctrl_stat	Signal
rst_por	ahci_ctrl_stat	Signal
rst_hba	ahci_ctrl_stat	Signal
rst_port	ahci_ctrl_stat	Signal
ghc_is_r	ahci_ctrl_stat	Signal
set_ghc_is_r	ahci_ctrl_stat	Signal
cleared_ghc	ahci_ctrl_stat	Signal
PxIE_r	ahci_ctrl_stat	Signal
PxIS_r	ahci_ctrl_stat	Signal
PxSSTS_r	ahci_ctrl_stat	Signal
PxSERR_r	ahci_ctrl_stat	Signal
PxCMD_r	ahci_ctrl_stat	Signal
pxci0_r	ahci_ctrl_stat	Signal
GHC_r	ahci_ctrl_stat	Signal
ghc_ie	ahci_ctrl_stat	Signal
cirq_PRC	ahci_ctrl_stat	Signal
cirq_PC	ahci_ctrl_stat	Signal
cirq	ahci_ctrl_stat	Signal
sirq	ahci_ctrl_stat	Signal
serr	ahci_ctrl_stat	Signal
sssts_ipm	ahci_ctrl_stat	Signal
sssts_spd	ahci_ctrl_stat	Signal
sssts_det	ahci_ctrl_stat	Signal
pcmd_clear_icc_r	ahci_ctrl_stat	Signal
pcmd_clear_icc	ahci_ctrl_stat	Signal
set_ssts_ipm	ahci_ctrl_stat	Signal
set_ssts_spd	ahci_ctrl_stat	Signal
set_ssts_det	ahci_ctrl_stat	Signal
set_pxcmd	ahci_ctrl_stat	Signal
pxci_changed	ahci_ctrl_stat	Signal
ssts_changed	ahci_ctrl_stat	Signal
serr_changed	ahci_ctrl_stat	Signal
sirq_changed	ahci_ctrl_stat	Signal
pxcmd_changed	ahci_ctrl_stat	Signal
ghc_is_changed	ahci_ctrl_stat	Signal
ghc_ghc_changed	ahci_ctrl_stat	Signal
regs_changed	ahci_ctrl_stat	Signal
updating	ahci_ctrl_stat	Signal
update_first	ahci_ctrl_stat	Signal
update_next	ahci_ctrl_stat	Signal
update_GHC__IS	ahci_ctrl_stat	Signal
update_HBA_PORT__PxIS	ahci_ctrl_stat	Signal
update_HBA_PORT__PxSSTS	ahci_ctrl_stat	Signal
update_HBA_PORT__PxSERR	ahci_ctrl_stat	Signal
update_HBA_PORT__PxCMD	ahci_ctrl_stat	Signal
update_HBA_PORT__PxCI	ahci_ctrl_stat	Signal
update_GHC_GHC	ahci_ctrl_stat	Signal
pfsm_started_r	ahci_ctrl_stat	Signal
unsolicited_en_r	ahci_ctrl_stat	Signal
PxIE_MASK	ahci_ctrl_stat	Parameter
PxIS_MASK	ahci_ctrl_stat	Parameter
PxSERR_MASK	ahci_ctrl_stat	Parameter
PxCMD_DFLT	ahci_ctrl_stat	Parameter
PxCMD_MASK	ahci_ctrl_stat	Parameter
mrst	ahci_dma	Input
hrst	ahci_dma	Input
mclk	ahci_dma	Input
hclk	ahci_dma	Input
ctba	ahci_dma	Input
ctba_ld	ahci_dma	Input
prdtl	ahci_dma	Input
dev_wr	ahci_dma	Input
cmd_start	ahci_dma	Input
prd_start	ahci_dma	Input
cmd_abort	ahci_dma	Input
axi_wr_cache_mode	ahci_dma	Input
axi_rd_cache_mode	ahci_dma	Input
set_axi_wr_cache_mode	ahci_dma	Input
set_axi_rd_cache_mode	ahci_dma	Input
ct_busy	ahci_dma	Output
ct_addr	ahci_dma	Input
ct_re	ahci_dma	Input
ct_data	ahci_dma	Output
prd_done	ahci_dma	Output
prd_irq_clear	ahci_dma	Input
prd_irq_pend	ahci_dma	Output
cmd_busy	ahci_dma	Output
cmd_done	ahci_dma	Output
abort_busy	ahci_dma	Output
abort_done	ahci_dma	Output
axi_mismatch	ahci_dma	Output
sys_out	ahci_dma	Output
sys_dav	ahci_dma	Output
sys_re	ahci_dma	Input
last_h2d_data	ahci_dma	Output
sys_in	ahci_dma	Input
sys_nfull	ahci_dma	Output
sys_we	ahci_dma	Input
extra_din	ahci_dma	Output
afi_awaddr	ahci_dma	Output
afi_awvalid	ahci_dma	Output
afi_awready	ahci_dma	Input
afi_awid	ahci_dma	Output
afi_awlock	ahci_dma	Output
afi_awcache	ahci_dma	Output
afi_awprot	ahci_dma	Output
afi_awlen	ahci_dma	Output
afi_awsize	ahci_dma	Output
afi_awburst	ahci_dma	Output
afi_awqos	ahci_dma	Output
afi_wdata	ahci_dma	Output
afi_wvalid	ahci_dma	Output
afi_wready	ahci_dma	Input
afi_wid	ahci_dma	Output
afi_wlast	ahci_dma	Output
afi_wstrb	ahci_dma	Output
afi_bvalid	ahci_dma	Input
afi_bready	ahci_dma	Output
afi_bid	ahci_dma	Input
afi_bresp	ahci_dma	Input
afi_wcount	ahci_dma	Input
afi_wacount	ahci_dma	Input
afi_wrissuecap1en	ahci_dma	Output
afi_araddr	ahci_dma	Output
afi_arvalid	ahci_dma	Output
afi_arready	ahci_dma	Input
afi_arid	ahci_dma	Output
afi_arlock	ahci_dma	Output
afi_arcache	ahci_dma	Output
afi_arprot	ahci_dma	Output
afi_arlen	ahci_dma	Output
afi_arsize	ahci_dma	Output
afi_arburst	ahci_dma	Output
afi_arqos	ahci_dma	Output
afi_rdata	ahci_dma	Input
afi_rvalid	ahci_dma	Input
afi_rready	ahci_dma	Output
afi_rid	ahci_dma	Input
afi_rlast	ahci_dma	Input
afi_rresp	ahci_dma	Input
afi_rcount	ahci_dma	Input
afi_racount	ahci_dma	Input
afi_rdissuecap1en	ahci_dma	Output
debug_out	ahci_dma	Output
debug_out1	ahci_dma	Output
debug_dma_h2d	ahci_dma	Output
SAFE_RD_BITS	ahci_dma	Parameter
ct_data_ram	ahci_dma	Signal
int_data_addr	ahci_dma	Signal
ctba_r	ahci_dma	Signal
prdtl_mclk	ahci_dma	Signal
cmd_start_hclk	ahci_dma	Signal
prd_start_r	ahci_dma	Signal
prd_start_hclk	ahci_dma	Signal
prd_start_hclk_r	ahci_dma	Signal
cmd_abort_hclk	ahci_dma	Signal
prd_enabled	ahci_dma	Signal
ct_over_prd_enabled	ahci_dma	Signal
ct_maddr	ahci_dma	Signal
ct_done	ahci_dma	Signal
first_prd_fetch	ahci_dma	Signal
afi_addr	ahci_dma	Signal
axi_set_raddr_ready	ahci_dma	Signal
axi_set_waddr_ready	ahci_dma	Signal
axi_set_raddr_w	ahci_dma	Signal
axi_set_waddr_w	ahci_dma	Signal
axi_set_addr_data_w	ahci_dma	Signal
axi_set_raddr_r	ahci_dma	Signal
axi_set_waddr_r	ahci_dma	Signal
is_ct_addr	ahci_dma	Signal
is_prd_addr	ahci_dma	Signal
is_data_addr	ahci_dma	Signal
data_addr	ahci_dma	Signal
data_len	ahci_dma	Signal
data_irq	ahci_dma	Signal
wcount	ahci_dma	Signal
wcount_set	ahci_dma	Signal
qwcount	ahci_dma	Signal
qwcount_done	ahci_dma	Signal
qw_datawr_left	ahci_dma	Signal
qw_datawr_burst	ahci_dma	Signal
qw_datawr_last	ahci_dma	Signal
data_afi_re	ahci_dma	Signal
prds_left	ahci_dma	Signal
last_prd	ahci_dma	Signal
afi_rd_ctl	ahci_dma	Signal
ct_busy_r	ahci_dma	Signal
prd_rd_busy	ahci_dma	Signal
dev_wr_mclk	ahci_dma	Signal
dev_wr_hclk	ahci_dma	Signal
prd_wr	ahci_dma	Signal
prd_rd	ahci_dma	Signal
afi_wstb4	ahci_dma	Signal
done_dev_wr	ahci_dma	Signal
done_dev_rd	ahci_dma	Signal
prd_done_hclk	ahci_dma	Signal
done_flush	ahci_dma	Signal
cmd_done_hclk	ahci_dma	Signal
ct_done_mclk	ahci_dma	Signal
afi_alen	ahci_dma	Signal
afi_wcount_many	ahci_dma	Signal
data_next_burst	ahci_dma	Signal
raddr_prd_rq	ahci_dma	Signal
raddr_prd_pend	ahci_dma	Signal
raddr_ct_rq	ahci_dma	Signal
raddr_ct_pend	ahci_dma	Signal
addr_data_rq_w	ahci_dma	Signal
addr_data_rq_r	ahci_dma	Signal
waddr_data_rq	ahci_dma	Signal
raddr_data_rq	ahci_dma	Signal
waddr_data_pend	ahci_dma	Signal
raddr_data_pend	ahci_dma	Signal
ct_id	ahci_dma	Signal
prd_id	ahci_dma	Signal
dev_wr_id	ahci_dma	Signal
dev_rd_id	ahci_dma	Signal
afi_id	ahci_dma	Signal
fifo_nempty_mclk	ahci_dma	Signal
en_extra_din_r	ahci_dma	Signal
ct_data_reg	ahci_dma	Signal
hrst_r	ahci_dma	Signal
abort_or_reset	ahci_dma	Signal
afi_dirty	ahci_dma	Signal
afi_dirty_mclk	ahci_dma	Signal
abort_done_hclk	ahci_dma	Signal
abort_done_mclk	ahci_dma	Signal
abort_done_unneeded	ahci_dma	Signal
aborting	ahci_dma	Signal
afi_wvalid_data	ahci_dma	Signal
afi_wvalid_abort	ahci_dma	Signal
afi_wid_abort	ahci_dma	Signal
afi_rready_abort	ahci_dma	Signal
afi_wlast_abort	ahci_dma	Signal
abort_rq_mclk	ahci_dma	Signal
abort_busy_mclk	ahci_dma	Signal
abort_debug	ahci_dma	Signal
rwaddr_rq_r	ahci_dma	Signal
debug_01	ahci_dma	Signal
debug_02	ahci_dma	Signal
debug_03	ahci_dma	Signal
wcount_plus_data_addr	ahci_dma	Signal
dbg_afi_awvalid_cntr	ahci_dma	Signal
dbg_qwcount	ahci_dma	Signal
dbg_qwcount_cntr	ahci_dma	Signal
dbg_set_raddr_count	ahci_dma	Signal
dbg_set_waddr_count	ahci_dma	Signal
dbg_was_mismatch	ahci_dma	Signal
ADDRESS_BITS	ahci_fis_receive	Parameter
hba_rst	ahci_fis_receive	Input
mclk	ahci_fis_receive	Input
pcmd_st_cleared	ahci_fis_receive	Input
fis_first_vld	ahci_fis_receive	Output
fis_first_invalid	ahci_fis_receive	Output
fis_first_flush	ahci_fis_receive	Input
get_dsfis	ahci_fis_receive	Input
get_psfis	ahci_fis_receive	Input
get_rfis	ahci_fis_receive	Input
get_sdbfis	ahci_fis_receive	Input
get_ufis	ahci_fis_receive	Input
get_data_fis	ahci_fis_receive	Input
get_ignore	ahci_fis_receive	Input
get_fis_busy	ahci_fis_receive	Output
get_fis_done	ahci_fis_receive	Output
fis_ok	ahci_fis_receive	Output
fis_err	ahci_fis_receive	Output
fis_ferr	ahci_fis_receive	Output
dma_prds_done	ahci_fis_receive	Input
fis_extra	ahci_fis_receive	Output
set_update_sig	ahci_fis_receive	Input
pUpdateSig	ahci_fis_receive	Output
sig_available	ahci_fis_receive	Output
update_sig	ahci_fis_receive	Input
update_err_sts	ahci_fis_receive	Input
update_pio	ahci_fis_receive	Input
update_prdbc	ahci_fis_receive	Input
clear_prdbc	ahci_fis_receive	Input
clear_bsy_drq	ahci_fis_receive	Input
clear_bsy_set_drq	ahci_fis_receive	Input
set_bsy	ahci_fis_receive	Input
set_sts_7f	ahci_fis_receive	Input
set_sts_80	ahci_fis_receive	Input
clear_xfer_cntr	ahci_fis_receive	Input
decr_dwcr	ahci_fis_receive	Input
decr_dwcw	ahci_fis_receive	Input
decr_DXC_dw	ahci_fis_receive	Input
pcmd_fre	ahci_fis_receive	Input
pPioXfer	ahci_fis_receive	Output
tfd_sts	ahci_fis_receive	Output
tfd_err	ahci_fis_receive	Output
fis_i	ahci_fis_receive	Output
sdb_n	ahci_fis_receive	Output
dma_a	ahci_fis_receive	Output
dma_d	ahci_fis_receive	Output
pio_i	ahci_fis_receive	Output
pio_d	ahci_fis_receive	Output
pio_es	ahci_fis_receive	Output
sactive0	ahci_fis_receive	Output
xfer_cntr	ahci_fis_receive	Output
xfer_cntr_zero	ahci_fis_receive	Output
data_in_dwords	ahci_fis_receive	Output
reg_addr	ahci_fis_receive	Output
reg_we	ahci_fis_receive	Output
reg_data	ahci_fis_receive	Output
hba_data_in	ahci_fis_receive	Input
hba_data_in_type	ahci_fis_receive	Input
hba_data_in_valid	ahci_fis_receive	Input
hba_data_in_many	ahci_fis_receive	Input
hba_data_in_ready	ahci_fis_receive	Output
dma_in_ready	ahci_fis_receive	Input
dma_in_valid	ahci_fis_receive	Output
debug_data_in_ready	ahci_fis_receive	Output
debug_fis_end_w	ahci_fis_receive	Output
debug_fis_end_r	ahci_fis_receive	Output
debug_get_fis_busy_r	ahci_fis_receive	Output
CLB_OFFS32	ahci_fis_receive	Parameter
HBA_OFFS32	ahci_fis_receive	Parameter
HBA_PORT0_OFFS32	ahci_fis_receive	Parameter
PXSIG_OFFS32	ahci_fis_receive	Parameter
PXTFD_OFFS32	ahci_fis_receive	Parameter
FB_OFFS32	ahci_fis_receive	Parameter
DSFIS32	ahci_fis_receive	Parameter
PSFIS32	ahci_fis_receive	Parameter
RFIS32	ahci_fis_receive	Parameter
SDBFIS32	ahci_fis_receive	Parameter
UFIS32	ahci_fis_receive	Parameter
DSFIS32_LENM1	ahci_fis_receive	Parameter
PSFIS32_LENM1	ahci_fis_receive	Parameter
RFIS32_LENM1	ahci_fis_receive	Parameter
SDBFIS32_LENM1	ahci_fis_receive	Parameter
UFIS32_LENM1	ahci_fis_receive	Parameter
DMAH_LENM1	ahci_fis_receive	Parameter
IGNORE_LENM1	ahci_fis_receive	Parameter
DATA_TYPE_DMA	ahci_fis_receive	Parameter
DATA_TYPE_FIS_HEAD	ahci_fis_receive	Parameter
DATA_TYPE_OK	ahci_fis_receive	Parameter
DATA_TYPE_ERR	ahci_fis_receive	Parameter
xfer_cntr_zero_r	ahci_fis_receive	Signal
dma_in_start	ahci_fis_receive	Signal
dma_in_stop	ahci_fis_receive	Signal
dma_skipping_extra	ahci_fis_receive	Signal
dma_in	ahci_fis_receive	Signal
was_data_in	ahci_fis_receive	Signal
data_in_dwords_r	ahci_fis_receive	Signal
dwords_over	ahci_fis_receive	Signal
too_long_err	ahci_fis_receive	Signal
reg_addr_r	ahci_fis_receive	Signal
fis_dcount	ahci_fis_receive	Signal
fis_save	ahci_fis_receive	Signal
is_fis_end	ahci_fis_receive	Signal
fis_end_w	ahci_fis_receive	Signal
fis_end_r	ahci_fis_receive	Signal
fis_rec_run	ahci_fis_receive	Signal
is_data_fis	ahci_fis_receive	Signal
is_ignore	ahci_fis_receive	Signal
is_FIS_HEAD	ahci_fis_receive	Signal
is_FIS_NOT_HEAD	ahci_fis_receive	Signal
data_in_ready	ahci_fis_receive	Signal
get_fis	ahci_fis_receive	Signal
wreg_we_r	ahci_fis_receive	Signal
reg_we_w	ahci_fis_receive	Signal
store_sig	ahci_fis_receive	Signal
reg_ds	ahci_fis_receive	Signal
reg_ps	ahci_fis_receive	Signal
reg_d2h	ahci_fis_receive	Signal
reg_sdb	ahci_fis_receive	Signal
xfer_cntr_r	ahci_fis_receive	Signal
prdbc_r	ahci_fis_receive	Signal
tf_err_sts	ahci_fis_receive	Signal
update_err_sts_r	ahci_fis_receive	Signal
update_sig_r	ahci_fis_receive	Signal
update_prdbc_r	ahci_fis_receive	Signal
get_fis_busy_r	ahci_fis_receive	Signal
pio_es_r	ahci_fis_receive	Signal
pio_err_r	ahci_fis_receive	Signal
pUpdateSig_r	ahci_fis_receive	Signal
sig_r	ahci_fis_receive	Signal
fis_extra_r	ahci_fis_receive	Signal
fis_first_invalid_r	ahci_fis_receive	Signal
fis_first_flushing_r	ahci_fis_receive	Signal
PREFETCH_ALWAYS	ahci_fis_transmit	Parameter
READ_REG_LATENCY	ahci_fis_transmit	Parameter
READ_CT_LATENCY	ahci_fis_transmit	Parameter
ADDRESS_BITS	ahci_fis_transmit	Parameter
hba_rst	ahci_fis_transmit	Input
mclk	ahci_fis_transmit	Input
pcmd_st_cleared	ahci_fis_transmit	Input
fetch_cmd	ahci_fis_transmit	Input
cfis_xmit	ahci_fis_transmit	Input
dx_xmit	ahci_fis_transmit	Input
atapi_xmit	ahci_fis_transmit	Input
done	ahci_fis_transmit	Output
busy	ahci_fis_transmit	Output
clearCmdToIssue	ahci_fis_transmit	Input
pCmdToIssue	ahci_fis_transmit	Output
xmit_ok	ahci_fis_transmit	Input
xmit_err	ahci_fis_transmit	Input
syncesc_recv	ahci_fis_transmit	Input
xrdy_collision	ahci_fis_transmit	Input
dx_err	ahci_fis_transmit	Output
ch_prdtl	ahci_fis_transmit	Output
ch_c	ahci_fis_transmit	Output
ch_b	ahci_fis_transmit	Output
ch_r	ahci_fis_transmit	Output
ch_p	ahci_fis_transmit	Output
ch_w	ahci_fis_transmit	Output
ch_a	ahci_fis_transmit	Output
ch_cfl	ahci_fis_transmit	Output
dwords_sent	ahci_fis_transmit	Output
reg_addr	ahci_fis_transmit	Output
reg_re	ahci_fis_transmit	Output
reg_rdata	ahci_fis_transmit	Input
xfer_cntr	ahci_fis_transmit	Input
xfer_cntr_zero	ahci_fis_transmit	Input
dma_ctba_ld	ahci_fis_transmit	Output
dma_start	ahci_fis_transmit	Output
dma_dev_wr	ahci_fis_transmit	Output
dma_ct_busy	ahci_fis_transmit	Input
dma_prd_start	ahci_fis_transmit	Output
dma_cmd_abort	ahci_fis_transmit	Output
ct_addr	ahci_fis_transmit	Output
ct_re	ahci_fis_transmit	Output
ct_data	ahci_fis_transmit	Input
dma_out	ahci_fis_transmit	Input
dma_dav	ahci_fis_transmit	Input
dma_re	ahci_fis_transmit	Output
last_h2d_data	ahci_fis_transmit	Input
todev_data	ahci_fis_transmit	Output
todev_type	ahci_fis_transmit	Output
todev_valid	ahci_fis_transmit	Output
todev_ready	ahci_fis_transmit	Input
debug_01	ahci_fis_transmit	Output
CLB_OFFS32	ahci_fis_transmit	Parameter
DATA_FIS	ahci_fis_transmit	Parameter
todev_full_r	ahci_fis_transmit	Signal
dma_en_r	ahci_fis_transmit	Signal
fis_data_valid	ahci_fis_transmit	Signal
fis_data_type	ahci_fis_transmit	Signal
fis_data_out	ahci_fis_transmit	Signal
write_or_w	ahci_fis_transmit	Signal
dma_re_w	ahci_fis_transmit	Signal
ch_prdtl_r	ahci_fis_transmit	Signal
ch_c_r	ahci_fis_transmit	Signal
ch_b_r	ahci_fis_transmit	Signal
ch_r_r	ahci_fis_transmit	Signal
ch_p_r	ahci_fis_transmit	Signal
ch_w_r	ahci_fis_transmit	Signal
ch_a_r	ahci_fis_transmit	Signal
ch_cmd_len_r	ahci_fis_transmit	Signal
cfis_acmd_left_r	ahci_fis_transmit	Signal
cfis_acmd_left_out_r	ahci_fis_transmit	Signal
reg_re_r	ahci_fis_transmit	Signal
reg_re_w	ahci_fis_transmit	Signal
pre_reg_stb	ahci_fis_transmit	Signal
fetch_chead_r	ahci_fis_transmit	Signal
fetch_chead_stb_r	ahci_fis_transmit	Signal
chead_done_w	ahci_fis_transmit	Signal
chead_bsy	ahci_fis_transmit	Signal
chead_bsy_re	ahci_fis_transmit	Signal
pCmdToIssue_r	ahci_fis_transmit	Signal
acfis_xmit_pend_r	ahci_fis_transmit	Signal
acfis_xmit_start_r	ahci_fis_transmit	Signal
acfis_xmit_busy_r	ahci_fis_transmit	Signal
acfis_xmit_start_w	ahci_fis_transmit	Signal
acfis_xmit_end	ahci_fis_transmit	Signal
ct_re_w	ahci_fis_transmit	Signal
ct_re_r	ahci_fis_transmit	Signal
ct_stb	ahci_fis_transmit	Signal
fis_dw_first	ahci_fis_transmit	Signal
fis_dw_last	ahci_fis_transmit	Signal
dx_dwords_left	ahci_fis_transmit	Signal
dx_fis_pend_r	ahci_fis_transmit	Signal
dx_dma_last_w	ahci_fis_transmit	Signal
dx_busy_r	ahci_fis_transmit	Signal
dx_err_r	ahci_fis_transmit	Signal
xmit_ok_r	ahci_fis_transmit	Signal
any_cmd_start	ahci_fis_transmit	Signal
done_w	ahci_fis_transmit	Signal
fetch_cmd_busy_r	ahci_fis_transmit	Signal
dbg_was_ct_re_r	ahci_fis_transmit	Signal
dbg_was_cfis_acmd_left_r	ahci_fis_transmit	Signal
hba_rst	ahci_fsm	Input
mclk	ahci_fsm	Input
was_hba_rst	ahci_fsm	Input
was_port_rst	ahci_fsm	Input
aclk	ahci_fsm	Input
arst	ahci_fsm	Input
pgm_ad	ahci_fsm	Input
pgm_wa	ahci_fsm	Input
pgm_wd	ahci_fsm	Input
phy_ready	ahci_fsm	Input
syncesc_send	ahci_fsm	Output
syncesc_send_done	ahci_fsm	Input
comreset_send	ahci_fsm	Output
cominit_got	ahci_fsm	Input
set_offline	ahci_fsm	Output
send_R_OK	ahci_fsm	Output
send_R_ERR	ahci_fsm	Output
pfsm_started	ahci_fsm	Output
update_all	ahci_fsm	Output
update_busy	ahci_fsm	Input
pcmd_cr_set	ahci_fsm	Output
pcmd_cr_reset	ahci_fsm	Output
pcmd_clo	ahci_fsm	Input
pcmd_st	ahci_fsm	Input
pcmd_st_cleared	ahci_fsm	Input
sirq_TFE	ahci_fsm	Output
sirq_IF	ahci_fsm	Output
sirq_INF	ahci_fsm	Output
sirq_OF	ahci_fsm	Output
sirq_PRC	ahci_fsm	Output
sirq_PC	ahci_fsm	Output
sirq_DP	ahci_fsm	Output
sirq_UF	ahci_fsm	Output
sirq_SDB	ahci_fsm	Output
sirq_DS	ahci_fsm	Output
sirq_PS	ahci_fsm	Output
sirq_DHR	ahci_fsm	Output
serr_diag_X	ahci_fsm	Input
ssts_ipm_dnp	ahci_fsm	Output
ssts_ipm_active	ahci_fsm	Output
ssts_ipm_part	ahci_fsm	Output
ssts_ipm_slumb	ahci_fsm	Output
ssts_ipm_devsleep	ahci_fsm	Output
ssts_spd_dnp	ahci_fsm	Output
ssts_spd_gen1	ahci_fsm	Output
ssts_spd_gen2	ahci_fsm	Output
ssts_spd_gen3	ahci_fsm	Output
ssts_det_ndnp	ahci_fsm	Output
ssts_det_dnp	ahci_fsm	Output
ssts_det_dp	ahci_fsm	Output
ssts_det_offline	ahci_fsm	Output
ssts_det	ahci_fsm	Input
sctl_det	ahci_fsm	Input
sctl_det_changed	ahci_fsm	Input
sctl_det_reset	ahci_fsm	Output
hba_rst_done	ahci_fsm	Output
pxci0_clear	ahci_fsm	Output
pxci0	ahci_fsm	Input
dma_prd_irq_clear	ahci_fsm	Output
dma_prd_irq_pend	ahci_fsm	Input
dma_cmd_busy	ahci_fsm	Input
dma_cmd_abort	ahci_fsm	Output
dma_abort_done	ahci_fsm	Input
fis_first_invalid	ahci_fsm	Input
fis_first_flush	ahci_fsm	Output
fis_first_vld	ahci_fsm	Input
fis_type	ahci_fsm	Input
bist_bits	ahci_fsm	Input
get_dsfis	ahci_fsm	Output
get_psfis	ahci_fsm	Output
get_rfis	ahci_fsm	Output
get_sdbfis	ahci_fsm	Output
get_ufis	ahci_fsm	Output
get_data_fis	ahci_fsm	Output
get_ignore	ahci_fsm	Output
get_fis_done	ahci_fsm	Input
fis_ok	ahci_fsm	Input
fis_err	ahci_fsm	Input
fis_ferr	ahci_fsm	Input
fis_extra	ahci_fsm	Input
set_update_sig	ahci_fsm	Output
update_sig	ahci_fsm	Output
update_err_sts	ahci_fsm	Output
update_pio	ahci_fsm	Output
update_prdbc	ahci_fsm	Output
clear_bsy_drq	ahci_fsm	Output
clear_bsy_set_drq	ahci_fsm	Output
set_bsy	ahci_fsm	Output
set_sts_7f	ahci_fsm	Output
set_sts_80	ahci_fsm	Output
clear_xfer_cntr	ahci_fsm	Output
decr_dwcr	ahci_fsm	Output
decr_dwcw	ahci_fsm	Output
pxcmd_fre	ahci_fsm	Input
pPioXfer	ahci_fsm	Input
tfd_sts	ahci_fsm	Input
fis_i	ahci_fsm	Input
dma_a	ahci_fsm	Input
pio_i	ahci_fsm	Input
pio_d	ahci_fsm	Input
xfer_cntr_zero	ahci_fsm	Input
fetch_cmd	ahci_fsm	Output
cfis_xmit	ahci_fsm	Output
dx_xmit	ahci_fsm	Output
atapi_xmit	ahci_fsm	Output
xmit_done	ahci_fsm	Input
clearCmdToIssue	ahci_fsm	Output
pCmdToIssue	ahci_fsm	Input
dx_err	ahci_fsm	Input
ch_c	ahci_fsm	Input
ch_b	ahci_fsm	Input
ch_r	ahci_fsm	Input
ch_p	ahci_fsm	Input
ch_w	ahci_fsm	Input
ch_a	ahci_fsm	Input
unsolicited_en	ahci_fsm	Input
last_jump_addr	ahci_fsm	Output
LABEL_POR	ahci_fsm	Parameter
LABEL_HBA_RST	ahci_fsm	Parameter
LABEL_PORT_RST	ahci_fsm	Parameter
LABEL_COMINIT	ahci_fsm	Parameter
LABEL_ST_CLEARED	ahci_fsm	Parameter
tfd_bsy	ahci_fsm	Signal
tfd_drq	ahci_fsm	Signal
tfd_sts_err	ahci_fsm	Signal
pgm_waddr	ahci_fsm	Signal
cond_met_w	ahci_fsm	Signal
pgm_jump_addr	ahci_fsm	Signal
pgm_addr	ahci_fsm	Signal
pgm_data	ahci_fsm	Signal
was_rst	ahci_fsm	Signal
fsm_jump	ahci_fsm	Signal
fsm_next	ahci_fsm	Signal
fsm_actions	ahci_fsm	Signal
dis_actions	ahci_fsm	Signal
fsm_act_busy	ahci_fsm	Signal
fsm_transitions	ahci_fsm	Signal
fsm_preload	ahci_fsm	Signal
pre_jump_w	ahci_fsm	Signal
fsm_act_done_w	ahci_fsm	Signal
fsm_act_done	ahci_fsm	Signal
fsm_act_pre_done	ahci_fsm	Signal
fsm_wait_act_w	ahci_fsm	Signal
fsm_last_act_w	ahci_fsm	Signal
fsm_pre_act_w	ahci_fsm	Signal
async_pend_r	ahci_fsm	Signal
async_from_st	ahci_fsm	Signal
asynq_rq	ahci_fsm	Signal
async_ackn	ahci_fsm	Signal
syncesc_send_pend	ahci_fsm	Signal
phy_ready_prev	ahci_fsm	Signal
phy_ready_chng_r	ahci_fsm	Signal
phy_ready_chng_w	ahci_fsm	Signal
was_last_action_r	ahci_fsm	Signal
fsm_transitions_w	ahci_fsm	Signal
conditions_ce	ahci_fsm	Signal
pisn32	ahci_fsm	Signal
clear_pisn32	ahci_fsm	Signal
PREFETCH_ALWAYS	ahci_top
READ_REG_LATENCY	ahci_top
READ_CT_LATENCY	ahci_top
ADDRESS_BITS	ahci_top
HBA_RESET_BITS	ahci_top
RESET_TO_FIRST_ACCESS	ahci_top
FREQ_METER_WIDTH	ahci_top
aclk	ahci_top
arst	ahci_top
mclk	ahci_top
mrst	ahci_top
hba_arst	ahci_top
port_arst	ahci_top
port_arst_any	ahci_top
hclk	ahci_top
hrst	ahci_top
awaddr	ahci_top
awvalid	ahci_top
awready	ahci_top
awid	ahci_top
awlen	ahci_top
awsize	ahci_top
awburst	ahci_top
wdata	ahci_top
wvalid	ahci_top
wready	ahci_top
wid	ahci_top
wlast	ahci_top
wstb	ahci_top
bvalid	ahci_top
bready	ahci_top
bid	ahci_top
bresp	ahci_top
araddr	ahci_top
arvalid	ahci_top
arready	ahci_top
arid	ahci_top
arlen	ahci_top
arsize	ahci_top
arburst	ahci_top
rdata	ahci_top
rvalid	ahci_top
rready	ahci_top
rid	ahci_top
rlast	ahci_top
rresp	ahci_top
afi_awaddr	ahci_top
afi_awvalid	ahci_top
afi_awready	ahci_top
afi_awid	ahci_top
afi_awlock	ahci_top
afi_awcache	ahci_top
afi_awprot	ahci_top
afi_awlen	ahci_top
afi_awsize	ahci_top
afi_awburst	ahci_top
afi_awqos	ahci_top
afi_wdata	ahci_top
afi_wvalid	ahci_top
afi_wready	ahci_top
afi_wid	ahci_top
afi_wlast	ahci_top
afi_wstrb	ahci_top
afi_bvalid	ahci_top
afi_bready	ahci_top
afi_bid	ahci_top
afi_bresp	ahci_top
afi_wcount	ahci_top
afi_wacount	ahci_top
afi_wrissuecap1en	ahci_top
afi_araddr	ahci_top
afi_arvalid	ahci_top
afi_arready	ahci_top
afi_arid	ahci_top
afi_arlock	ahci_top
afi_arcache	ahci_top
afi_arprot	ahci_top
afi_arlen	ahci_top
afi_arsize	ahci_top
afi_arburst	ahci_top
afi_arqos	ahci_top
afi_rdata	ahci_top
afi_rvalid	ahci_top
afi_rready	ahci_top
afi_rid	ahci_top
afi_rlast	ahci_top
afi_rresp	ahci_top
afi_rcount	ahci_top
afi_racount	ahci_top
afi_rdissuecap1en	ahci_top
h2d_data	ahci_top
h2d_type	ahci_top
h2d_valid	ahci_top
h2d_ready	ahci_top
d2h_data	ahci_top
d2h_type	ahci_top
d2h_valid	ahci_top
d2h_many	ahci_top
d2h_ready	ahci_top
phy_ready	ahci_top
xmit_ok	ahci_top
xmit_err	ahci_top
syncesc_recv	ahci_top
pcmd_st_cleared	ahci_top
syncesc_send	ahci_top
syncesc_send_done	ahci_top
comreset_send	ahci_top
cominit_got	ahci_top
set_offline	ahci_top
x_rdy_collision	ahci_top
send_R_OK	ahci_top
send_R_ERR	ahci_top
serr_DT	ahci_top
serr_DS	ahci_top
serr_DH	ahci_top
serr_DC	ahci_top
serr_DB	ahci_top
serr_DW	ahci_top
serr_DI	ahci_top
serr_EE	ahci_top
serr_EP	ahci_top
serr_EC	ahci_top
serr_ET	ahci_top
serr_EM	ahci_top
serr_EI	ahci_top
sctl_ipm	ahci_top
sctl_spd	ahci_top
irq	ahci_top
datascope1_clk	ahci_top
datascope1_waddr	ahci_top
datascope1_we	ahci_top
datascope1_di	ahci_top
drp_en	ahci_top
drp_we	ahci_top
drp_addr	ahci_top
drp_di	ahci_top
drp_rdy	ahci_top
drp_do	ahci_top
xclk_period	ahci_top
debug_in_phy	ahci_top
debug_in_link	ahci_top
datascope_clk	ahci_top
datascope_waddr	ahci_top
datascope_we	ahci_top
datascope_di	ahci_top
soft_write_addr	ahci_top
soft_write_data	ahci_top
soft_write_en	ahci_top
regs_we_acs	ahci_top
regs_din_from_acs	ahci_top
regs_we_freceive	ahci_top
regs_re_ftransmit	ahci_top
regs_saddr	ahci_top
regs_waddr	ahci_top
regs_raddr	ahci_top
regs_din_from_freceive	ahci_top
regs_dout	ahci_top
en_port	ahci_top
regs_re	ahci_top
regs_we	ahci_top
regs_addr	ahci_top
regs_din	ahci_top
ctba_ld	ahci_top
prdtl	ahci_top
dev_wr	ahci_top
dma_cmd_start	ahci_top
dma_prd_start	ahci_top
dma_cmd_abort_xmit	ahci_top
dma_cmd_abort_fsm	ahci_top
fsm_pgm_ad	ahci_top
fsm_pgm_wa	ahci_top
fsm_pgm_wd	ahci_top
axi_wr_cache_mode	ahci_top
axi_rd_cache_mode	ahci_top
set_axi_cache_mode	ahci_top
dma_ct_busy	ahci_top
dma_ct_addr	ahci_top
dma_ct_re	ahci_top
dma_ct_data	ahci_top
dma_prd_irq_clear	ahci_top
dma_prd_irq_pend	ahci_top
dma_cmd_busy	ahci_top
dma_cmd_done	ahci_top
dma_abort_busy	ahci_top
dma_abort_done	ahci_top
axi_mismatch	ahci_top
dma_dout	ahci_top
dma_dav	ahci_top
dma_re	ahci_top
last_h2d_data	ahci_top
dma_in_ready	ahci_top
dma_we	ahci_top
dma_extra_din	ahci_top
frcv_first_vld	ahci_top
frcv_first_invalid	ahci_top
frcv_first_flush	ahci_top
frcv_get_dsfis	ahci_top
frcv_get_psfis	ahci_top
frcv_get_rfis	ahci_top
frcv_get_sdbfis	ahci_top
frcv_get_ufis	ahci_top
frcv_get_data_fis	ahci_top
frcv_get_ignore	ahci_top
frcv_update_err_sts	ahci_top
frcv_update_pio	ahci_top
frcv_update_prdbc	ahci_top
frcv_clear_bsy_drq	ahci_top
frcv_clear_bsy_set_drq	ahci_top
frcv_set_bsy	ahci_top
frcv_set_sts_7f	ahci_top
frcv_set_sts_80	ahci_top
frcv_decr_dwcr	ahci_top
frcv_decr_dwcw	ahci_top
frcv_clear_xfer_cntr	ahci_top
frcv_busy	ahci_top
frcv_done	ahci_top
frcv_ok	ahci_top
frcv_err	ahci_top
frcv_ferr	ahci_top
frcv_extra	ahci_top
frcv_set_update_sig	ahci_top
frcv_update_sig	ahci_top
tfd_sts	ahci_top
fis_i	ahci_top
dma_a	ahci_top
pio_i	ahci_top
pio_d	ahci_top
pPioXfer	ahci_top
xfer_cntr	ahci_top
xfer_cntr_zero	ahci_top
fsnd_fetch_cmd	ahci_top
fsnd_cfis_xmit	ahci_top
fsnd_dx_xmit	ahci_top
fsnd_atapi_xmit	ahci_top
fsnd_done	ahci_top
fsnd_clearCmdToIssue	ahci_top
fsnd_pCmdToIssue	ahci_top
fsnd_dx_err	ahci_top
fsnd_ch_c	ahci_top
fsnd_ch_b	ahci_top
fsnd_ch_r	ahci_top
fsnd_ch_p	ahci_top
fsnd_ch_w	ahci_top
fsnd_ch_a	ahci_top
data_out_dwords	ahci_top
was_hba_rst	ahci_top
was_port_rst	ahci_top
update_all_regs	ahci_top
update_regs_busy	ahci_top
pcmd_esp	ahci_top
pcmd_cr_set	ahci_top
pcmd_cr_reset	ahci_top
pcmd_fre0	ahci_top
pcmd_fre	ahci_top
pcmd_clo	ahci_top
pcmd_st	ahci_top
pfsm_started	ahci_top
sirq_TFE	ahci_top
sirq_IF	ahci_top
sirq_INF	ahci_top
sirq_OF	ahci_top
sirq_PRC	ahci_top
sirq_PC	ahci_top
sirq_DP	ahci_top
sirq_UF	ahci_top
sirq_SDB	ahci_top
sirq_DS	ahci_top
sirq_PS	ahci_top
sirq_DHR	ahci_top
serr_diag_X	ahci_top
ssts_ipm_dnp	ahci_top
ssts_ipm_active	ahci_top
ssts_ipm_part	ahci_top
ssts_ipm_slumb	ahci_top
ssts_ipm_devsleep	ahci_top
ssts_spd_dnp	ahci_top
ssts_spd_gen1	ahci_top
ssts_spd_gen2	ahci_top
ssts_spd_gen3	ahci_top
ssts_det_ndnp	ahci_top
ssts_det_dnp	ahci_top
ssts_det_dp	ahci_top
ssts_det_offline	ahci_top
ssts_det	ahci_top
sctl_det	ahci_top
sctl_det_changed	ahci_top
sctl_det_reset	ahci_top
pxci0_clear	ahci_top
pxci0	ahci_top
hba_rst_done	ahci_top
comreset_send0	ahci_top
last_jump_addr	ahci_top
debug_dma	ahci_top
debug_dma1	ahci_top
debug_dma_h2d	ahci_top
unsolicited_en	ahci_top
debug_data_in_ready	ahci_top
debug_fis_end_w	ahci_top
debug_fis_end_r	ahci_top
debug_get_fis_busy_r	ahci_top
DATA_TYPE_DMA	ahci_top
DATA_TYPE_FIS_HEAD	ahci_top
DATA_TYPE_OK	ahci_top
DATA_TYPE_ERR	ahci_top
debug_d2h_length	ahci_top
debug_d2h_length_prev	ahci_top
was_good_bad	ahci_top
was_good_bad_prev	ahci_top
ahci_fis_transmit_busy	ahci_top
xmit_dbg_01	ahci_top
ADDRESS_BITS	datascope_timing	Parameter
FIS_LEN	datascope_timing	Parameter
clk	datascope_timing	Input
rst	datascope_timing	Input
soft_write_addr	datascope_timing	Input
soft_write_data	datascope_timing	Input
soft_write_en	datascope_timing	Input
h2d_data	datascope_timing	Input
h2d_type	datascope_timing	Input
h2d_valid	datascope_timing	Input
h2d_ready	datascope_timing	Input
d2h_data	datascope_timing	Input
d2h_type	datascope_timing	Input
d2h_valid	datascope_timing	Input
d2h_ready	datascope_timing	Input
datascope_clk	datascope_timing	Output
datascope_waddr	datascope_timing	Output
datascope_we	datascope_timing	Output
datascope_di	datascope_timing	Output
punch_tag	datascope_timing	Signal
write_tag_w	datascope_timing	Signal
pend_punch_time	datascope_timing	Signal
write_punch_time	datascope_timing	Signal
fis_run	datascope_timing	Signal
fis_run_d	datascope_timing	Signal
fis_we	datascope_timing	Signal
fis_len	datascope_timing	Signal
fis_left	datascope_timing	Signal
fis_data	datascope_timing	Signal
cur_time	datascope_timing	Signal
was_h2d_last	datascope_timing	Signal
fis_start	datascope_timing	Signal
fis_end	datascope_timing	Signal
pre_we_w	datascope_timing	Signal
pre_we_r	datascope_timing	Signal
we_r	datascope_timing	Signal
ADDRESS_BITS	axi_ahci_regs	Parameter
HBA_RESET_BITS	axi_ahci_regs	Parameter
RESET_TO_FIRST_ACCESS	axi_ahci_regs	Parameter
aclk	axi_ahci_regs	Input
arst	axi_ahci_regs	Input
awaddr	axi_ahci_regs	Input
awvalid	axi_ahci_regs	Input
awready	axi_ahci_regs	Output
awid	axi_ahci_regs	Input
awlen	axi_ahci_regs	Input
awsize	axi_ahci_regs	Input
awburst	axi_ahci_regs	Input
wdata	axi_ahci_regs	Input
wvalid	axi_ahci_regs	Input
wready	axi_ahci_regs	Output
wid	axi_ahci_regs	Input
wlast	axi_ahci_regs	Input
wstb	axi_ahci_regs	Input
bvalid	axi_ahci_regs	Output
bready	axi_ahci_regs	Input
bid	axi_ahci_regs	Output
bresp	axi_ahci_regs	Output
araddr	axi_ahci_regs	Input
arvalid	axi_ahci_regs	Input
arready	axi_ahci_regs	Output
arid	axi_ahci_regs	Input
arlen	axi_ahci_regs	Input
arsize	axi_ahci_regs	Input
arburst	axi_ahci_regs	Input
rdata	axi_ahci_regs	Output
rvalid	axi_ahci_regs	Output
rready	axi_ahci_regs	Input
rid	axi_ahci_regs	Output
rlast	axi_ahci_regs	Output
rresp	axi_ahci_regs	Output
soft_write_addr	axi_ahci_regs	Output
soft_write_data	axi_ahci_regs	Output
soft_write_en	axi_ahci_regs	Output
hba_arst	axi_ahci_regs	Output
port_arst	axi_ahci_regs	Output
port_arst_any	axi_ahci_regs	Output
hba_clk	axi_ahci_regs	Input
hba_rst	axi_ahci_regs	Input
hba_addr	axi_ahci_regs	Input
hba_we	axi_ahci_regs	Input
hba_re	axi_ahci_regs	Input
hba_din	axi_ahci_regs	Input
hba_dout	axi_ahci_regs	Output
pgm_ad	axi_ahci_regs	Output
pgm_wa	axi_ahci_regs	Output
pgm_wd	axi_ahci_regs	Output
afi_wcache	axi_ahci_regs	Output
afi_rcache	axi_ahci_regs	Output
afi_cache_set	axi_ahci_regs	Output
was_hba_rst	axi_ahci_regs	Output
was_port_rst	axi_ahci_regs	Output
debug_in0	axi_ahci_regs	Input
debug_in1	axi_ahci_regs	Input
debug_in2	axi_ahci_regs	Input
debug_in3	axi_ahci_regs	Input
drp_en	axi_ahci_regs	Output
drp_we	axi_ahci_regs	Output
drp_addr	axi_ahci_regs	Output
drp_di	axi_ahci_regs	Output
drp_rdy	axi_ahci_regs	Input
drp_do	axi_ahci_regs	Input
datascope_clk	axi_ahci_regs	Input
datascope_waddr	axi_ahci_regs	Input
datascope_we	axi_ahci_regs	Input
datascope_di	axi_ahci_regs	Input
datascope1_clk	axi_ahci_regs	Input
datascope1_waddr	axi_ahci_regs	Input
datascope1_we	axi_ahci_regs	Input
datascope1_di	axi_ahci_regs	Input
DRP_ADDR	axi_ahci_regs	Parameter
drp_read_data	axi_ahci_regs	Signal
drp_read_r	axi_ahci_regs	Signal
drp_ready_r	axi_ahci_regs	Signal
AXIBRAM_BITS	axi_ahci_regs	Parameter
datascope_rdata	axi_ahci_regs	Signal
datascope_sel	axi_ahci_regs	Signal
datascope1_rdata	axi_ahci_regs	Signal
datascope1_sel	axi_ahci_regs	Signal
bram_waddr	axi_ahci_regs	Signal
bram_raddr	axi_ahci_regs	Signal
bram_rdata	axi_ahci_regs	Signal
pre_bram_wen	axi_ahci_regs	Signal
bram_wen	axi_ahci_regs	Signal
bram_wstb	axi_ahci_regs	Signal
bram_wdata	axi_ahci_regs	Signal
bram_addr	axi_ahci_regs	Signal
bram_ren	axi_ahci_regs	Signal
write_busy_r	axi_ahci_regs	Signal
write_start_burst	axi_ahci_regs	Signal
write_busy_w	axi_ahci_regs	Signal
bram_wdata_r	axi_ahci_regs	Signal
bram_rdata_r	axi_ahci_regs	Signal
regbit_type	axi_ahci_regs	Signal
ahci_regs_di	axi_ahci_regs	Signal
bram_wstb_r	axi_ahci_regs	Signal
bram_wen_r	axi_ahci_regs	Signal
wmask	axi_ahci_regs	Signal
bram_waddr_r	axi_ahci_regs	Signal
hba_reset_cntr	axi_ahci_regs	Signal
hba_rst_r	axi_ahci_regs	Signal
port_rst_r	axi_ahci_regs	Signal
port_arst_any_r	axi_ahci_regs	Signal
high_sel	axi_ahci_regs	Signal
afi_cache_set_w	axi_ahci_regs	Signal
pgm_fsm_set_w	axi_ahci_regs	Signal
pgm_fsm_and_w	axi_ahci_regs	Signal
set_hba_rst	axi_ahci_regs	Signal
HBA_PORT__PxSCTL__DET__MASK01	axi_ahci_regs	Parameter
set_port_rst	axi_ahci_regs	Signal
port_rst_on	axi_ahci_regs	Signal
was_hba_rst_aclk	axi_ahci_regs	Signal
was_port_rst_aclk	axi_ahci_regs	Signal
was_hba_rst_r	axi_ahci_regs	Signal
was_port_rst_r	axi_ahci_regs	Signal
arst_r	axi_ahci_regs	Signal
wait_first_access	axi_ahci_regs	Signal
any_access	axi_ahci_regs	Signal
debug_rd_r	axi_ahci_regs	Signal
debug_r	axi_ahci_regs	Signal
action_decoder	ahci_fsm	Module Instance
ahci_ctrl_stat	ahci_top
ahci_defaults.vh	axi_ahci_regs	Include
ahci_dma	ahci_top
ahci_dma_rd_fifo	ahci_dma	Module Instance
ahci_dma_wr_fifo	ahci_dma	Module Instance
ahci_fis_receive	ahci_top
ahci_fis_transmit	ahci_top
ahci_fsm	ahci_top
ahci_fsm.ahci_localparams.vh	ahci_fsm	Include
axi_ahci_regs.ahci_localparams.vh	axi_ahci_regs	Include
ahci_ctrl_stat.ahci_localparams.vh	ahci_ctrl_stat	Include
ahci_fis_receive.ahci_localparams.vh	ahci_fis_receive	Include
datascope_timing.ahci_localparams.vh	datascope_timing	Include
ahci_types.vh	axi_ahci_regs	Include
ahxi_fsm_code.vh	ahci_fsm	Include
ahci_dma.ALWAYS_532 src_clk or rst	pulse_cross_clock	Always Construct
ahci_dma.pulse_cross_clock.ALWAYS_532 src_clk or rst	pulse_cross_clock	Always Construct
ahci_dma.ALWAYS_533 dst_clk	pulse_cross_clock	Always Construct
ahci_dma.pulse_cross_clock.ALWAYS_533 dst_clk	pulse_cross_clock	Always Construct
ALWAYS_558 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_559 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_560 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_561 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_562 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_563 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_564 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_565 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_566 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_567 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_568 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_569 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_570 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_571 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_572 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_573 mclk	ahci_ctrl_stat	Always Construct
ALWAYS_574 mclk	ahci_dma	Always Construct
ALWAYS_575 hclk	ahci_dma	Always Construct
ALWAYS_576 hclk	ahci_dma	Always Construct
ALWAYS_583 mclk	ahci_fis_receive	Always Construct
ALWAYS_584 mclk	ahci_fis_transmit	Always Construct
ALWAYS_585 aclk	ahci_fsm	Always Construct
ALWAYS_586 mclk	ahci_fsm	Always Construct
ALWAYS_587 mclk	ahci_fsm	Always Construct
ALWAYS_591 mrst or mclk	ahci_top	Always Construct
ALWAYS_592 mclk	ahci_top	Always Construct
ALWAYS_593 clk	datascope_timing	Always Construct
ALWAYS_594 aclk	axi_ahci_regs	Always Construct
ALWAYS_595 aclk	axi_ahci_regs	Always Construct
ALWAYS_596 aclk	axi_ahci_regs	Always Construct
ALWAYS_597 aclk	axi_ahci_regs	Always Construct
ALWAYS_598 hba_clk	axi_ahci_regs	Always Construct
ALWAYS_599 aclk	axi_ahci_regs	Always Construct
ALWAYS_600 aclk	axi_ahci_regs	Always Construct
axi_ahci_regs	ahci_top
axi_hp_abort	ahci_dma	Module Instance
axibram_read	axi_ahci_regs	Module Instance
axibram_write	axi_ahci_regs	Module Instance
condition_mux	ahci_fsm	Module Instance
DATASCOPE_FIS_DATA	ahci_top
datascope_timing	ahci_top
fifo_cross_clocks	axi_ahci_regs	Module Instance
fis_types.vh	ahci_fsm	Include
GENERATE [284]	axi_ahci_regs	GENERATE
axi_ahci_regs.pulse_cross_clock	axi_ahci_regs	Module Instance
ahci_dma.pulse_cross_clock	ahci_dma	Module Instance
ram18p_var_w_var_r	ahci_fsm	Module Instance
ram_var_w_var_r	axi_ahci_regs	Module Instance
ram_var_w_var_r	axi_ahci_regs	Module Instance
ram_var_w_var_r	axi_ahci_regs	Module Instance
ramt_var_wb_var_r	axi_ahci_regs	Module Instance