52 input [
WCNT_BITS-
1:
0]
wcnt,
// decrementing word counter, 0- based (0 need 1, 1 - need 2, ...) valid @ start 53 input [
1:
0]
woffs,
// 2 LSBs of the initial word address - valid @ start 58 input last_prd,
// last prd, flush partial dword if there were odd number of words transferred. valid @ start 59 // Or maybe use "last_prd"? 61 output reg done,
// this PRD data sent to cross-clock FIFO (may result in only half-dword sent out), 62 // OK to fetch another PRD (if it was not the last) 63 output done_flush,
// finished last PRD (indicated by last_prd @ start), data left module 74 // reg [ADDRESS_BITS+1:0] raddr; // 1 extra bit 77 reg [
63:
16]
din_prev;
// only 48 bits are needed 102 // wire [63:0] fifo_do = fifo_ram [raddr[ADDRESS_BITS:1]]; 103 // wire [3:0] fifo_do_vld = vld_ram [raddr[ADDRESS_BITS:1]]; 122 // just for gtkwave - same names 128 // assign fifo_dav2_w = fifo_full2[raddr[ADDRESS_BITS:1]] ^ raddr[ADDRESS_BITS+1]; 129 /// assign fifo_dav2_w = fifo_full2[raddr_r[ADDRESS_BITS:1]] ^ raddr_r[ADDRESS_BITS+1]; 169 // if (fifo_wr) flush_ram[waddr[ADDRESS_BITS-1:0]] <= fifo_di_flush; 186 // if (mrst) raddr <= 0; 187 // else if (fifo_rd) raddr <= raddr + 1; 192 // else if (fifo_rd && raddr[0]) fifo_nempty <= {fifo_nempty[ADDRESS_NUM-2:0], ~raddr[ADDRESS_BITS+1] ^ raddr[ADDRESS_BITS]}; 195 // fifo_dav <= fifo_full [raddr[ADDRESS_BITS:1]] ^ raddr[ADDRESS_BITS+1]; 196 /// fifo_dav <= fifo_full [raddr_r[ADDRESS_BITS:1]] ^ raddr_r[ADDRESS_BITS+1]; 217 // .din (raddr[0]?fifo_do[63:32]: fifo_do[31:0]), // input[31:0] 218 // .dm (raddr[0]?fifo_do_vld[3:2]:fifo_do_vld[1:0]), // input[1:0]
done_flush_i pulse_cross_clock
13025ADDRESS_NUM(1<<ADDRESS_BITS
13028raddr_wwire[ADDRESS_BITS+1:0]
13048fifo_di_vldwire[3:0]
13060raddrwire[ADDRESS_BITS+1:0]
13026waddrreg[ADDRESS_BITS:0]
13050fifo_do_vld_rreg[3:0]
ahci_dma_rd_stuff_i ahci_dma_rd_stuff
13062fifo_do_vldwire[3:0]
13058debug_waddrwire[2:0]
13041fifo_full2wire[1<<ADDRESS_BITS-1:0]
[0:ADDRESS_NUM-1] 13033fifo_ramreg[63:0]
13059debug_raddrwire[2:0]
[WCNT_BITS-1:0] 13010wcnt
13036fifo_nemptyreg[1<<ADDRESS_BITS-1:0]
13035fifo_fullreg[1<<ADDRESS_BITS-1:0]
13027raddr_rreg[ADDRESS_BITS+1:0]
13030qwcntrreg[WCNT_BITS-3:0]
[0:ADDRESS_NUM-1] 13034vld_ramreg[3:0]
[31:0] 13024debug_dma_h2d