57 input SDRST,
// DDR3 reset (active low) 58 input SDCLK,
// DDR3 clock differential output, positive 59 input SDNCLK,
// DDR3 clock differential output, negative 61 input [
2:
0]
SDBA,
// output bank address ports 62 input SDWE,
// output WE port 65 input SDCKE,
// output Clock Enable port 68 inout [
15:
0]
SDD,
// DQ I/O pads 69 input SDDML,
// LDM I/O pad (actually only output) 70 inout DQSL,
// LDQS I/O pad 72 input SDDMU,
// UDM I/O pad (actually only output) 73 inout DQSU,
// UDQS I/O pad 148 // wire [1:0] en_dq_out=en_dq_d2; 149 // wire [1:0] en_dqs_out=en_dqs_d2; 153 // wire [1:0] en_dq_in= ~en_dq_d0 & ~en_dq_d1 & ~en_dq_d2 & ~en_dq_d3 & ~en_dq_d4; 154 // wire [1:0] en_dqs_in=~en_dqs_d0 & ~en_dqs_d1 & ~en_dqs_d2 & ~en_dqs_d3 & ~en_dqs_d4; 156 wire [
1:
0]
en_dq_in= ~
en_dq_d0 & ~
en_dq_d1 & ~
en_dq_d2 & ~
en_dq_d3 & ~
en_dq_d4 & ~
en_dq_d5 & ~
en_dq_d6 & ~
en_dq_d7;
157 wire [
1:
0]
en_dqs_in=~
en_dqs_d0 & ~
en_dqs_d1 & ~
en_dqs_d2 & ~
en_dqs_d3 & ~
en_dqs_d4 & ~
en_dqs_d5 & ~
en_dqs_d6 & ~
en_dqs_d7;
160 /* Instance template for module dly_16 **/ 338 .TDQSCK_DLLDIS (400), 385 .TRFC_MAX (70200000), 429 .PRE_DEF_PAT (8'hAA), 433 .RANDOM_OUT_DELAY (0), 434 .RANDOM_SEED (31913), 443 .check_strict_mrbits (1), 444 .check_strict_timing (1), 446 .feature_truebl4 (0), 449 .LOAD_MODE (4'b0000), 451 .PRECHARGE (4'b0010), 468 .
rst_n (
SDRST_D),
// input 469 .
ck (
SDCLK_D),
// input 470 .
ck_n (
SDNCLK_D),
// input 471 .
cke (
SDCKE_D),
// input 472 .
cs_n (
1'b0),
// input 473 .
ras_n (
SDRAS_D),
// input 474 .
cas_n (
SDCAS_D),
// input 475 .
we_n (
SDWE_D),
// input 477 .
ba (
SDBA_D[
2:
0]),
// input[2:0] 478 .
addr (
SDA_D[
14:
0]),
// input[14:0] 479 .
dq (
SDD_D[
15:
0]),
// inout[15:0] 482 .
tdqs_n (),
// output[1:0] 483 .
odt (
SDODT_D)
// input
[ADDRESS_NUMBER-1:0] 11091SDA
11106CMDA_DELAY_HCMDA_DELAY/4
11105CLK_DELAY_HCLK_DELAY/4
11077TRISTATE_DELAY_CLK4'h2
11108DQ_IN_DELAY_HDQ_IN_DELAY/4
11109DQS_OUT_DELAY_HDQS_OUT_DELAY/4
11110DQ_OUT_DELAY_HDQ_OUT_DELAY/4
11107DQS_IN_DELAY_HDQS_IN_DELAY/4