00001 //x353.h 00002 // fpga definitions (should match those of Verilog sources) 00003 #define X313_MINMODREV 0x03534000 // minimal fpga model/rev that should work with current driver 00004 #define X313_MAXMODREV 0x035340ff // maximal fpga model/rev that should work with current driver 00005 00006 #define X313__RA__STATUS 0x10 // read status register 00007 #define X313__RA__IRQS 0x11 // read interrupt register 00008 #define X313__RA__TRIGPH 0x12 // read trigger phase (line/pixel of readout when trigger came) 00009 #define X313__RA__MODEL 0x13 // read model number/revision of FPGA 00010 #define X313__RA__TABLE 0x14 // readback FPGA tables (not all of them, may be removed later) 00011 00012 #define X313__RA__XFERCNTR 0x14 // readback compressor transfer counter (24 bits, counts 32-byutes chunks) 00013 #define X313__RA__HIGHFREQ 0x15 // 32-bit accumulated value oif hi-frequency components (filter is table defined) - (since 03533014) 00014 00015 00016 // #define X313__RA__USB 0x60 // read USB data 00017 #define X313__RA__IOPINS 0x70 // read state of 12 I/O pins 00018 // bit 0 - SCL1 00019 // bit 1 - SDA1 00020 // bit 2 - XRST 00021 // bit 3 - AUXCLK 00022 // bit 4 - EXPS 00023 // bit 5 - TRIG 00024 #define X313__RA__SENSFPGA 0x74 // - currently will read the same s0x70. Bit 16 (0x10000) is multiplexed state of 1 of 3 pins 00025 #define SFPGA_RD_BIT 16 // Obsolete???? 00026 #define I2C_FRAME_NUMBER 0x16 // Read 3 LSB of frame number as seen by I2C controller and i2c busy (0x10000) 00027 00028 00029 #define X313__RA__SDCH0 0x20 00030 #define X313__RA__SDCH1 0x24 00031 #define X313__RA__SDCH2 0x28 00032 #define X313__RA__SDCH3 0x2c 00033 #define X313__RA__SDBUF3 0x30 // 30.37 - data window for PIO access (channel3) 00034 00035 #define X313_SR__CLK_LOCKED 28 00036 #define X313_SR__SENS_DCM_OVFL 27 00037 #define X313_SR__SENS_DCM_LOCKED 26 00038 #define X313_SR__SENS_DCM_RDY 25 00039 00040 #define X313_SR__SENS_DCM_EARLY 24 00041 #define X313_SR__SENS_DCM_LATE 23 00042 // new meaning: 00043 #define X313_SR__SENS_DCM_ERROR 24 // if 0, the data strobe is in a middle of >= T/2 stable data (never the case with 96MHz at slow drivers) 00044 // if 1 - at least one of the before/after strobes return different data than the actual strobe 00045 #define X313_SR__SENS_DCM_LATE 23 // "1" - needs phase increase ( 80 for 90 degrees, 20 - for fine) 00046 00047 #define X313_SENSOR_PHASE ((port_csp0_addr[X313__RA__STATUS] >> X313_SR__SENS_DCM_LATE ) & 3) 00048 00049 00050 #define X313_SR__DCM_OVFL 22 00051 #define X313_SR__DCM_LOCKED 21 00052 #define X313_SR__DCM_RDY 20 00053 #define X313_SR__DCM_EARLY 19 00054 #define X313_SR__DCM_LATE 18 00055 00056 // #define X313_SR__TRIG 20 // TRIG input state 00057 #define X313_SR__DMA_EMPTY 17 // Dma buffer empty (wait after compressor is done) 00058 #define X313_SR__DONE_CMPRS 16 // Compressor done (IRQ available) 00059 #define X313_SR__DONE_CI 15 // Compressor finished reading SDRAM (IRQ available) 00060 #define X313_SR__DCCRDY 14 // Next 128 (or just the last in frame) DC components are ready 00061 // to be read out. 00062 #define X313_SR__DONE 13 // reset reset by writing to X313_WA_TRIG 00063 // 00 - off 00064 // 01 - waiting fo frame sync to start acquisition 00065 // 10 - waiting for trigger 00066 // 11 - acquisition in progr 00067 #define X313_SR__SENST1 12 00068 #define X313_SR__SENST0 11 00069 #define X313_SR__NXTFR3 10 00070 #define X313_SR__NXTFR2 9 00071 #define X313_SR__NXTFR1 8 00072 #define X313_SR__NXTFR0 7 00073 #define X313_SR__PIOWEMPTY 6 00074 #define X313_SR__PIORDY 5 00075 #define X313_SR__CH2RDY 4 00076 #define X313_SR__CH1RDY 3 00077 #define X313_SR__CH0RDY 2 00078 // #define X313_SR__SCL1 3 00079 // #define X313_SR__SDA1 2 00080 #define X313_SR__SCL0 1 00081 #define X313_SR__SDA0 0 00082 // Will chnage 00083 #define X313_PIOR__SCL1 0 00084 #define X313_PIOR__SDA1 1 00085 #define X313_PIOR__XRST 2 00086 #define X313_PIOR__AUXCLK 3 00087 #define X313_PIOR__EXPS 4 00088 #define X313_PIOR__TRIG 5 00089 00090 00091 00092 // valid for model 323 00093 #define X313_SR__X323_SI 0 00094 00095 00096 00097 #define X313_SR(x) ((port_csp0_addr[X313__RA__STATUS] >> X313_SR__##x ) & 1) 00098 #define X313_PIOR(x) ((port_csp0_addr[X313__RA__IOPINS] >> X313_PIOR__##x ) & 1) 00099 00100 00101 #define X313_IR__VACT 0 // start of VACT pulse 00102 #define X313_IR__XINT 1 // external enterrupt 00103 #define X313_IR__XFEROVR 2 // DMA xfer over 00104 #define X313_IR__DONE 3 // DMA xfer over, persistent till reset through... 00105 #define X313_IR__EOT 4 00106 #define X313_IR__DCC 5 // Next 128 16-bit DC components (and HF too) are ready (or the partial block - last in frame). 00107 // Reset when all 128 are read out or DCC mode is reset (0 is written to bit 12 register X313_WA_SDCH3_CTL0 - 0x2c) 00108 #define X313_IR__DONE_INPUT 6 // persistent till compressor reset/restarted 00109 #define X313_IR__DONE_COMPRESS 7 // persistent till compressor reset/restarted 00110 #define X313_IR__SMART 8 // Single cycle, does not need restart, configurable to wait for VACT, always at VACT if no compression is underway 00111 00112 #define X313_IR(x) ((port_csp0_addr[X313__RA__IRQS] >> ( X313_IR__##x ) + 8) & 1) 00113 00114 #define EN_INTERRUPT(x) port_csp0_addr[X313_WA_IRQ_ENA]= (1<< ( X313_IR__##x )) 00115 #define DIS_INTERRUPT(x) {port_csp0_addr[X313_WA_IRQ_DIS]= (1<< ( X313_IR__##x ) ); port_csp0_addr[X313_WA_IRQ_RST]= (1<< ( X313_IR__##x ) );} 00116 #define DIS_INTERRUPTS {port_csp0_addr[X313_WA_IRQ_DIS]= 0xffff; port_csp0_addr[X313_WA_IRQ_RST]= 0xffff;} 00117 00118 00119 /* peripherial write addresses (relative to csp0, in long words) */ 00120 #define X313_WA_WCTL 0 // write control register - 32 00121 #define X313_WA_DMACR 1 // DMA control register: 00122 // 17: DMA enable 00123 // 16: 0- raw, 1 - JPEG 00124 // 15-10: not used 00125 // 0-9: line length in long words 00126 #define X313_WA_SENSFPN 2 // Sensor/FPN control register: 00127 // 31-11: not used 00128 // [10] - testmode - if 1 generates gradient data (as Zoran chips) where pixel value = horizontal position 00129 // [9:7] - submode - subtract background (8 bits) mode (use di[7:0]): 00130 // 000 - no subtraction; 00131 // 001 - (finest) subtract 8 bit bkgnd from 12 bits pixels 00132 // 010 - shift 8bit bkgnd 1 bit left before applying 00133 // 011 - shift 8bit bkgnd 2 bits left before applying 00134 // 100 - shift 8bit bkgnd 2 bits left before applying 00135 // 101 - shift 8bit bkgnd 2 bits left before applying 00136 // fpn data to subtract should be a little less to add a "fat zero" 00137 // [6:4] - mpymode sensitivity correction mode (use di[15:8]): 00138 // 000 - no correction 00139 // 001 - fine correction (+/-3.125%) 00140 // 010 - fine correction (+/-6.25%) 00141 // 011 - fine correction (+/-12.5%) 00142 // 100 - +/- 25% 00143 // 101 - +/- 50% 00144 // [3] - wdth - word width: 0 - 8 bit, 1 - 16 bit (5 MSB == 0) 00145 // [2:0] scaling of 11 bit FPN result to fit in 8bit output: 00146 // 00 - default - use [9:1] 00147 // 01 - use [10:2] - to protect from saturation after applying mpymode 00148 // nominal range - 0..127 00149 // 10 - use [7:0] before saturation, "digital gain" == 4 (maximal) 00150 // 11 - use [8:1] before saturation, "digital gain" == 2 00151 // Result data is saturated by 255 00152 00153 #define X313_SENSFPN_D(t,s,m,d,l) (((t) & 1) << 10) | \ 00154 (((s) & 7) << 7) | \ 00155 (((m) & 7) << 4) | \ 00156 (((d) & 1) << 3) | \ 00157 (((l) & 7) << 0) 00158 00159 #define X313_WA_VIRTTRIG 3 // Virtual trigger threshold 00160 // 31-22 not used 00161 // 21-0 Trigger will fire if sum of pixels in a line 00162 // (after FPN processig) is more than this value. 00163 // Disabled if 0 - selected real (electrical) external trigger 00164 #define X313_WA_TRIG 4 // Sensor triggrring 00165 // 31-3: not used 00166 // 2: Enable sensor (0 - abort at once) 00167 // 1: External Trigger (0 - internal) 00168 // 0: continuous acquisition (0 - single "frame" - actually number of lines specified) 00169 #define X313_WA_NLINES 5 // number of lines to acquire (afer trigger) 00170 // 31-16: not used 00171 // 15 - select photofinish mode frames in one (1), nummber of lines (0) 00172 // 14 - not used 00173 // if photofinish ([15]==0) FIXME: change control in the driver, now FF mode is written separately 00174 // 13-0 : number of frames to combine it one (decimate frame sync pulses) 00175 // else ([15]==0) 00176 // 13-0 : number of lines to acquire (in a frame or after the external trigger) 00177 // 00178 #define X313_WA_WCTL24 6 // write control register - same as X313_WA_WCTL, but only 24 lower bits are affected 00179 00180 #define X313_WA_DCDC 7 // sensor DC-DC converter frequency settings 00181 // 31-05: not used 00182 // 4-0 0 - use internal clock (not sync) 00183 // 1..31 use divided pixel clock 00184 // for 20MHz use 5'h10, 00185 // else - N= (Fpix[MHz]/1.2)-1, if Fpix=20MHz, 00186 // N= 15.7->16=5'h10 00187 00188 #define X313_WA_DCM 8 // SDRAM clock phase shift 00189 // #define X3X3_RSTSENSDCM {port_csp0_addr[X313_WA_DCM]=0x30;} // needed after changing frequency to restart sensor DCM 00190 #define X3X3_RSTSENSDCM {port_csp0_addr[X313_WA_DCM]=0xf0;} // reset 90 degrees here too 00191 #define X3X3_SENSDCM_INC90 {port_csp0_addr[X313_WA_DCM]=0x80;} // switch clock phase in precise 90-degree increments 00192 #define X3X3_SENSDCM_DEC90 {port_csp0_addr[X313_WA_DCM]=0x40;} // switch clock phase in precise 90-degree increments 00193 // NOTE fine steps range is limited, combine with 90-degree steps when needed 00194 #define X3X3_SENSDCM_INC {port_csp0_addr[X313_WA_DCM]=0x20;} // switch clock phase in fine steps (~110 for 90 degrees @96MHz) 00195 #define X3X3_SENSDCM_DEC {port_csp0_addr[X313_WA_DCM]=0x10;} // switch clock phase in fine steps (~110 for 90 degrees @96MHz) 00196 #define X3X3_SENSDCM_NOP {port_csp0_addr[X313_WA_DCM]=0x0;} // resets DCM errors (before measuring sensor phase) 00197 00198 #define X313_WA_COLOR_SAT 9 // bits 9: 0 - Cb (blue) color saturation. 0x90 (default) for saturation =1.0 00199 // bits 21:12 - Cr (red) color saturation. 0xb6 (default) for saturation =1.0 00200 #define DEFAULT_COLOR_SATURATION_BLUE 0x90 // 100*realtive saturation blue 00201 #define DEFAULT_COLOR_SATURATION_RED 0xb6 // 100*realtive saturation red 00202 00203 #define X313_WA_FRAMESYNC_DLY 0x0a // Delay frame sync interrupt by number of lines (default - 0) 00204 #define X313_WA_QUANTIZER_MODE 0x0b // Quantizer tuning - 0..7 - zero bin, 15:8 - quantizer bias 00205 00206 #define X313_WA_COMP_CMD 0x0c 00207 // rev 7.2 control bits (written to X313_WA_COMP_CMD) 00208 // [23] ==1 - set focus mode 00209 // [22:21] 0 - none 00210 // 1 - replace 00211 // 2 - combine for all image 00212 // 3 - combine in window only 00213 #define COMPCMD_FOCUS(x) ((1<<23) | (((x) & 3) << 21)) 00214 00215 // [20] ==1 - set bayer shift (from the gammas) 00216 // [19:18] - bayer shift value (from the gammas) 00217 #define COMPCMD_BAYERSHIFT(x) ((1<<20) | (((x) & 3) << 18)) 00218 00219 // [17] == 1 - set processed tile position in the 20x20 tile got from memory 00220 // [16:14] 0 - top left alignment 00221 // 1 - 1 pixel right and 1 - down from the top left alignment 00222 // 2 - 2 pixels right and 2 - down from the top left alignment 00223 // 3 - 3 pixels right and 3 - down from the top left alignment 00224 // 4 - 4 pixels right and 4 - down from the top left alignment 00225 #define COMPCMD_TILESHIFT(x) ((1<<17) | (((x) & 7) << 14)) 00226 00227 // [13]==1 - enable color modes 00228 // [12:9]== 0 - monochrome, (4:2:0), 00229 // 1 - color, 4:2:0, 18x18(old) 00230 // 2 - jp4, original (4:2:0), 00231 // 3 - jp4, dc -improved (4:2:0), 00232 // 4 - color, 4:2:0, 20x20, middle of the tile (not yet implemented) 00233 // 5 - jp4, 4 blocks, (legacy) 00234 // 6 - jp4, 4 blocks, dc -improved 00235 // 7 - jp4, 4 blocks, differential red := (R-G1), blue:=(B-G1), green=G1, green2 (G2-G1). G1 is defined by Bayer shift, any pixel can be used 00236 // 8 - jp4, 4 blocks, differential HDR: red := (R-G1), blue:=(B-G1), green=G1, green2 (high gain)=G2) (G1 and G2 - diagonally opposite) 00237 // 9 - jp4, 4 blocks, differential, divide differences by 2: red := (R-G1)/2, blue:=(B-G1)/2, green=G1, green2 (G2-G1)/2 00238 // 10 - jp4, 4 blocks, differential HDR: red := (R-G1)/2, blue:=(B-G1)/2, green=G1, green2 (high gain)=G2), 00239 // 11-13 - reserved 00240 // 14 - mono, 4 blocks 00241 // 15 - reserved 00242 00243 #define COMPCMD_DEMOS(x) ((1<<13) | (((x) & 0x0f) << 9)) 00244 // 6 blocks output per macroblock: 00245 #define DEMOS_MONO6 0 // original monochrome YCbCr 4:2:0 with zeroed color components 00246 #define DEMOS_COLOR18 1 // original color YCbCr 4:2:0, 3x3 demosaic (18x18 tiles) 00247 #define DEMOS_JP46 2 // original jp4, (4:2:0, zero color), decoded by regular JPEG decoder 00248 #define DEMOS_JP46DC 3 // dc-improved: same as DEMOS_JP46, but DC difference separate for each component 00249 #define DEMOS_COLOR20 4 // color YCbCr 4:2:0, 5x5 demosaic (20x20 tiles) - not yet implemented 00250 // 4 blocks output per macroblock: 00251 #define DEMOS_JP4 5 // similar to DEMOS_JP46 , but zero color components are not output 00252 #define DEMOS_JP4DC 6 // similar to DEMOS_JP46DC , but zero color components are not output 00253 #define DEMOS_JP4DIFF 7 // differential red := (R-G1), blue:=(B-G1), green=G1, green2 (G2-G1). G1 is defined by Bayer shift, any pixel can be used 00254 #define DEMOS_JP4HDR 8 // similar to DEMOS_JP4DIFF, but second green (opposite from the reference one) is encoded without subtracting: 00255 // red := (R-G1), blue:=(B-G1), green=G1, green2 (high gain)=G2) (G1 and G2 - diagonally opposite) 00256 #define DEMOS_JP4DIFF2 9 // similar to DEMOS_JP4DIFF, but all differences are divided by 2 to fit into 8 bit range: 00257 // red := (R-G1)/2, blue:=(B-G1)/2, green=G1, green2 (G2-G1)/2 00258 #define DEMOS_JP4HDR2 10 // red := (R-G1)/2, blue:=(B-G1)/2, green=G1, green2 (high gain)=G2), 00259 #define DEMOS_MONO4 14 // monochrome, but the block scan order is still the same as in YCbCr 4:2:0 (macroblocks in scan order, block in 2x2 macroblock in scan order) 00260 00261 // [8:7] == 0,1 - NOP, 2 - disable, 3 - enable subtracting of average value (DC component), bypassing DCT 00262 00263 #define COMPCMD_DCSUB(x) ((1<<8) | (((x) & 1) << 7)) 00264 00265 // [6] == 1 - enable quantization bank select, 0 - disregard bits [5:3] 00266 // [5:3] = quantization page number (0..7) 00267 00268 #define COMPCMD_QTAB(x) ((1<<6) | (((x) & 7) << 3)) 00269 #define FPGA_NQTAB 8 // total number of quantization table pairs 00270 00271 #define COMPCMD_RESET 4 // reset compressor, stop immediately 00272 #define COMPCMD_STOP 5 // enable compressor, disable repetitive mode (will finish current frame) 00273 #define COMPCMD_SINGLE 6 // enable compressor, acquire single frame (will disable repetitive mode if it was set) 00274 #define COMPCMD_RUN 7 // enable repetitive mode 00275 // [2]== 1 - enable on/off control: 00276 // [1:0]== 0 - reset compressor, stop immediately 00277 // 1 - enable compressor, disable repetitive mode 00278 // 2 - enable compressor, compress single frame 00279 // 3 - enable compressor, enable repetitive mode 00280 // 00281 00282 #define X313_WA_COMP_TA 0x0e 00283 #define X313_WA_COMP_TD 0x0f 00284 #define X313_WA_MCUNUM 0x0d 00286 #define X313_WA_SMART_IRQ 0x1a 00287 00288 00289 #define X313_WA_DCM_RST 0x1b // async reset of the system DCM 00290 #define X313_WA_IRQ_RST 0x1c // reset selected interrupt bits 00291 #define X313_WA_IRQ_DIS 0x1d // disable selected interrupt bits (mask) 00292 #define X313_WA_IRQ_ENA 0x1e // enable selected interrupt bits 00293 #define X313_WA_IRQ_WVECT 0x1f // write vector number (in bits [0:7], [11:8] - interrupt number (0..15) 00294 00295 #define EN_INTERRUPT(x) port_csp0_addr[X313_WA_IRQ_ENA]= (1<< ( X313_IR__##x )) 00296 #define DIS_INTERRUPT(x) {port_csp0_addr[X313_WA_IRQ_DIS]= (1<< ( X313_IR__##x ) ); port_csp0_addr[X313_WA_IRQ_RST]= (1<< ( X313_IR__##x ) );} 00297 #define DIS_INTERRUPTS {port_csp0_addr[X313_WA_IRQ_DIS]= 0xffff; port_csp0_addr[X313_WA_IRQ_RST]= 0xffff;} 00298 00299 00300 // changed for rev 03533001f 00301 #define X313_WA_HIST_LEFT 0x40 00302 #define X313_WA_HIST_TOP 0x41 00303 #define X313_WA_HIST_WIDTH 0x42 00304 #define X313_WA_HIST_HEIGHT 0x43 00305 #define X313_WA_HIST_ADDR 0x44 00306 #define X313_RA_HIST_DATA 0x45 // use CSP4 with wait cycles to have a pulse (is timing for CSP4 now the same?) 00307 00308 #define X313_WA_RTC_USEC 0x48 00309 #define X313_WA_RTC_SEC 0x49 // sets both seconds and microseconds, so should be written second 00310 #define X313_WA_RTC_CORR 0x4a 00311 #define X313_WA_RTC_LATCH 0x4b 00312 #define X313_RA_RTC_USEC 0x48 00313 #define X313_RA_RTC_SEC 0x49 00314 #define X313_WA_TIMESTAMP 0x4c // 0 - no, 1 - normal frames, 2 - photofinish 00315 #define X313_TIMESTAMPLEN 28 // pixels used for timestamp 00316 00317 00318 #define X313_WA_DCR0 0x4e 00319 #define X313_WA_DCR1 0x4f 00324 #define X353_DCR0(x,y) (((((y) & ((1 << X353DCR0__##x##__WIDTH)-1))) | (1 << X353DCR0__##x##__WIDTH) ) << X353DCR0__##x##__BITNM) 00325 #define X353_DCR1(x,y) (((((y) & ((1 << X353DCR1__##x##__WIDTH)-1))) | (1 << X353DCR1__##x##__WIDTH) ) << X353DCR1__##x##__BITNM) 00326 00327 00329 #define X353DCR0__BAYER_PHASE__BITNM 0 00330 #define X353DCR0__BAYER_PHASE__WIDTH 2 00331 00332 #define X353DCR0__FILLFACTORY__BITNM 3 00333 #define X353DCR0__FILLFACTORY__WIDTH 1 00334 00335 #define X353DCR0__DLYHOR__BITNM 5 00336 #define X353DCR0__DLYHOR__WIDTH 1 00337 00338 #define X353DCR0__NEGRST__BITNM 7 // "zoran" 00339 #define X353DCR0__NEGRST__WIDTH 1 00340 00341 #define X353DCR0__SKIPLINEL__BITNM 9 00342 #define X353DCR0__SKIPLINE__WIDTH 1 00343 00344 #define X353DCR0__XT_POL__BITNM 11 00345 #define X353DCR0__XT_POL__WIDTH 1 00346 #define X353DCR0__ARST__BITNM 13 00347 #define X353DCR0__ARST__WIDTH 1 00348 #define X353DCR0__ARO__BITNM 15 00349 #define X353DCR0__ARO__WIDTH 1 00350 00351 // for 5MPix set - old sensors, reset - new ones 00352 #define X353DCR0__CNVEN__BITNM 17 00353 #define X353DCR0__CNVEN__WIDTH 1 00354 00355 #define X353DCR0__SENSTRIGEN__BITNM 19 00356 #define X353DCR0__SENSTRIGEN__WIDTH 1 00357 00359 #define X353DCR1__MRST__BITNM 0 00360 #define X353DCR1__MRST__WIDTH 1 00361 00362 // use start of trigger as a timestamp (in async mode to prevent timestamp jitter) 00363 #define X353DCR1__EARLYTRIG__BITNM 2 00364 #define X353DCR1__EARLYTRIG__WIDTH 1 00365 00366 //DCLKMODE - 0 - DCLK - clock to sensor, 1 - DCLK - input of conposite sync (from 10347) 00367 #define X353DCR1__DCLKMODE__BITNM 4 00368 #define X353DCR1__DCLKMODE__WIDTH 1 00369 00370 //PXD14 - 1 - 14-bit data from sensor 00371 #define X353DCR1__PXD14__BITNM 6 00372 #define X353DCR1__PXD14__WIDTH 1 00373 00374 #define X353DCR1__HACT_PHASE__BITNM 8 00375 #define X353DCR1__HACT_PHASE__WIDTH 2 00376 00377 // source of pixel clock. Now 0 - internal (CLK1), 1,2,3 - external (bpf) 00378 #define X353DCR1__PCLKSRC__BITNM 11 00379 #define X353DCR1__PCLKSRC__WIDTH 2 00380 00381 #define X353DCR1__HFCOMP__BITNM 14 00382 #define X353DCR1__HFCOMP__WIDTH 3 00383 00384 #define X353DCR1__BLOCKVSYNC__BITNM 18 00385 #define X353DCR1__BLOCKVSYNC__WIDTH 1 00386 00390 #define CCAM_ARO_ON port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARO,1) 00391 #define CCAM_ARO_OFF port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARO,0) 00393 #define CCAM_DCLK_OFF port_csp0_addr[X313_WA_DCR1]=X353_DCR1(DCLKMODE,1) 00394 #define CCAM_DCLK_ON port_csp0_addr[X313_WA_DCR1]=X353_DCR1(DCLKMODE,0) 00395 #define CCAM_ARST_OFF port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARST,1) 00396 #define CCAM_ARST_ON port_csp0_addr[X313_WA_DCR0]=X353_DCR0(ARST,0) 00397 #define CCAM_MRST_OFF port_csp0_addr[X313_WA_DCR1]=X353_DCR1(MRST,1) 00398 #define CCAM_MRST_ON port_csp0_addr[X313_WA_DCR1]=X353_DCR1(MRST,0) 00399 #define CCAM_NEGRST port_csp0_addr[X313_WA_DCR0]=X353_DCR0(NEGRST,1) 00400 #define CCAM_POSRST port_csp0_addr[X313_WA_DCR0]=X353_DCR0(NEGRST,0) 00402 #define CCAM_CNVEN_ON port_csp0_addr[X313_WA_DCR0]=X353_DCR0(CNVEN,1) 00403 #define CCAM_CNVEN_OFF port_csp0_addr[X313_WA_DCR0]=X353_DCR0(CNVEN,0) 00405 #define CCAM_TRIG_INT port_csp0_addr[X313_WA_DCR0]=X353_DCR0(SENSTRIGEN,0) 00406 #define CCAM_TRIG_EXT port_csp0_addr[X313_WA_DCR0]=X353_DCR0(SENSTRIGEN,1) 00408 #define CCAM_TIMESTAMP_NORMAL port_csp0_addr[X313_WA_DCR1]=X353_DCR1(EARLYTRIG,0) 00409 #define CCAM_TIMESTAMP_EARLY port_csp0_addr[X313_WA_DCR1]=X353_DCR1(EARLYTRIG,1) 00411 #define CCAM_SET_HACT_PHASE(x) port_csp0_addr[X313_WA_DCR1]=X353_DCR1(HACT_PHASE,(x)) 00412 00417 #define CCAM_VSYNC_ON port_csp0_addr[X313_WA_DCR1]=X353_DCR1(BLOCKVSYNC,0) 00418 #define CCAM_VSYNC_OFF port_csp0_addr[X313_WA_DCR1]=X353_DCR1(BLOCKVSYNC,1) 00419 00421 00423 00424 // following registers accept 32-bit data words to be sent as 4 (or less) i2c command, that consists of 00425 // start, slave address (MSB), register address (bits 16..23), and 2 bytes of data (MSB first). 00426 // For single-byte registers LSB of the data word is not used, data byte uses bits 8..15 00427 // Example 0x902b0010 - write 0x0010 to register 0x2b of slave 0x90 00428 // Writes use relative (to the current frame) and absolute (modulo 8) addresses (readable through I2C_FRAME_NUMBER) 00429 // When using absolute addressing writing to the frame one before current will effectively write to the current frame, 00430 // so if new frame happens during writing - data will not be lost - it will transferred to the next frame. 00431 // Each frame buffer can hold 63 commands, current frame can process unlimited number of commands as long as FIFO does not have 00432 // more than 63 at any given moment. 00433 00434 00435 #define X313_I2C_FRAME0 0x50 // write command to be sent at frame number 0 (modulo 8) - see I2C_FRAME_NUMBER, 3 LSBs 00436 #define X313_I2C_FRAME1 0x51 // same for frame number 1 00437 #define X313_I2C_FRAME2 0x52 // same for frame number 1 00438 #define X313_I2C_FRAME3 0x53 // same for frame number 1 00439 #define X313_I2C_FRAME4 0x54 // same for frame number 1 00440 #define X313_I2C_FRAME5 0x55 // same for frame number 1 00441 #define X313_I2C_FRAME6 0x56 // same for frame number 1 00442 #define X313_I2C_FRAME7 0x57 // same for frame number 1 00443 #define X313_I2C_ASAP 0x58 // write command to be sent to sensor ASAP 00444 #define X313_I2C_NEXT 0x59 // write command to be sent after next frame starts 00445 #define X313_I2C_NEXT2 0x5a // write command to be sent after next 2 frames start 00446 #define X313_I2C_NEXT3 0x5b // write command to be sent after next 2 frames start 00447 #define X313_I2C_NEXT4 0x5c // write command to be sent after next 2 frames start 00448 #define X313_I2C_NEXT5 0x5d // write command to be sent after next 2 frames start 00449 #define X313_I2C_NEXT6 0x5e // write command to be sent after next 2 frames start 00450 #define X313_I2C_CMD 0x5f // write command to i2c controller, command consists of several independent bit fields 00451 // below data that can be written to port_csp0_addr[X313_I2C_CMD], OR-ed 00452 #define X3X3_SET_I2C_DLY(x) (0x100 | ((x) & 0xff)) 00453 #define X3X3_SET_I2C_BYTES(x) (0x800 | (((x)<<9) & 0x600)) 00454 #define X3X3_I2C_RUN_BITS 0x3000 // can not be combined with X3X3_I2C_RESET 00455 #define X3X3_I2C_STOP_BITS 0x2000 00456 #define X3X3_I2C_RESET_BITS 0x4000 00458 #define X3X3_I2C_SCL_0_BITS 0x10000 00459 #define X3X3_I2C_SCL_1_BITS 0x20000 00460 #define X3X3_I2C_SCL_Z_BITS 0x30000 00461 #define X3X3_I2C_SDA_0_BITS 0x40000 00462 #define X3X3_I2C_SDA_1_BITS 0x80000 00463 #define X3X3_I2C_SDA_Z_BITS 0xc0000 00464 00465 #define X3X3_I2C_IS_BUSY (((port_csp0_addr[I2C_FRAME_NUMBER] | \ 00466 port_csp0_addr[I2C_FRAME_NUMBER] | \ 00467 port_csp0_addr[I2C_FRAME_NUMBER] | \ 00468 port_csp0_addr[I2C_FRAME_NUMBER] | \ 00469 port_csp0_addr[I2C_FRAME_NUMBER] ) & 0x10000)?1:0) 00470 #define X3X3_I2C_FRAME (port_csp0_addr[I2C_FRAME_NUMBER] & 0x7) 00471 #define X3X3_I2C_SEND2(a,s,r,d) {port_csp0_addr[a] = ((s)<<24) | (((r) & 0xff) << 16) | ((d) & 0xffff) ; X3X3_AFTERWRITE ;} 00472 #define X3X3_I2C_SEND1(a,s,r,d) {port_csp0_addr[a] = ((s)<<24) | (((r) & 0xff) << 16) | (((d) & 0xff) << 8) ; X3X3_AFTERWRITE ;} 00473 00474 #define X3X3_GAMMA_PAGE ((port_csp0_addr[I2C_FRAME_NUMBER] & 0x20000)?1:0) // gamma table page (0/1) currently used 00476 #define X3X3_I2C_STOP_WAIT {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_STOP_BITS; while (X3X3_I2C_IS_BUSY) ; } 00477 #define X3X3_I2C_RUN {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_RUN_BITS ; X3X3_AFTERWRITE ;} 00478 #define X3X3_I2C_RESET_WAIT {port_csp0_addr[X313_I2C_CMD]=X3X3_I2C_RESET_BITS; while (X3X3_I2C_IS_BUSY) ; } 00479 00480 00481 #define X313_SEQ_FRAME0 0x60 // write command to be sent at frame number 0 (modulo 8) - see CMD_FRAME_NUMBER, LSBs, bits [5:3] 00482 #define X313_SEQ_FRAME1 0x61 // same for frame number 1 00483 #define X313_SEQ_FRAME2 0x62 // same for frame number 2 00484 #define X313_SEQ_FRAME3 0x63 // same for frame number 3 00485 #define X313_SEQ_FRAME4 0x64 // same for frame number 4 00486 #define X313_SEQ_FRAME5 0x65 // same for frame number 5 00487 #define X313_SEQ_FRAME6 0x66 // same for frame number 6 00488 #define X313_SEQ_FRAME7 0x67 // same for frame number 7 00489 #define X313_SEQ_ASAP 0x68 // write command to be sent ASAP 00490 #define X313_SEQ_NEXT 0x69 // write command to be sent after next frame starts 00491 #define X313_SEQ_NEXT2 0x6a // write command to be sent after next 2 frames start 00492 #define X313_SEQ_NEXT3 0x6b // write command to be sent after next 3 frames start 00493 #define X313_SEQ_NEXT4 0x6c // write command to be sent after next 4 frames start 00494 #define X313_SEQ_NEXT5 0x6d // write command to be sent after next 5 frames start 00495 #define X313_SEQ_NEXT6 0x6e // write command to be sent after next 6 frames start 00496 #define X313_SEQ_CMD 0x6f // write command to i2c controller, command consists of several independent bit fields 00497 00498 #define X3X3_SEQ_RUN_BITS 0x3000 // can not be combined with X3X3_I2C_RESET 00499 #define X3X3_SEQ_STOP_BITS 0x2000 00500 #define X3X3_SEQ_RESET_BITS 0x4000 00501 00502 #define X3X3_SEQ_SEND1(f,a,d) {port_csp0_addr[f] = ((a)<<24) | ((d) & 0xffffff) ; X3X3_AFTERWRITE ;} 00503 00504 #define X3X3_SEQ_STOP {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_STOP_BITS;} 00505 #define X3X3_SEQ_RUN {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_RUN_BITS ; X3X3_AFTERWRITE ;} 00506 #define X3X3_SEQ_RESET {port_csp0_addr[X313_SEQ_CMD]=X3X3_SEQ_RESET_BITS; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; X3X3_AFTERWRITE ; } 00507 00508 00509 // [14] - reset all FIFO (takes 16 clock pulses), stop i2c until run command (can not be combined with "run") 00510 // [13] - if 1 - use [12] to run/stop i2c controller (needed to be stopped and confirmed not busy before software i2c) 00511 // [12] - run/stop i2c (when [13] == 1 00512 // [11] - if 1, use [10:9] to set command bytes to send after slave address (0..3) 00513 // [10:9] - number of bytes to send, valid if [11] is set. For Micron sensors - use 3 00514 // [8] - set duration of quarter i2c cycle in system clock cycles - nominal value 100 (0x64) for 160MHz 00515 // [7:0] - duration of quarter i2c cycle (applied if [8] is set) 00516 00517 00518 // #define X313_WA_USB 0x60 // ... 0x6f 00519 #define X313_WA_IOPINS 0x70 // bits [27:26] select the source of the control word: 00520 // to eliminate the need for a shadow registers made that a 00521 // dibit=0 - no change 00522 // dibit=1 - set en=1, d=0 00523 // dibit=2 - set en=1, d=1 00524 // dibit=3 - set en=0, d=0 00525 // 0 - use bits [25:0] of the control word (0 - data0, 1 - enable out0, 2 - data1, ..., 11 - enable out5) 00526 // 1 - use channel A (USB)? 00527 // 2 - use channel B (tbd) 00528 // 3 - use channel C (tbd) 00529 #define X313_WA_SENSFPGA 0x74 //Control programming of external FPGA on the sensor/sensor multiplexor board 00530 #define X313_WA_CAMSYNCTRIG 0x78 // trigger condition, 0 - internal, else dibits ((use<<1) | level) for each GPIO[11:0] pin 00531 #define X313_WA_CAMSYNCDLY 0x79 // trigger delay, 32 bits in pixel clocks 00532 #define X313_WA_CAMSYNCOUT 0x7a // trigger output to GPIO, dibits ((use << 1) | level_when_active). Bit 24 - test mode, when GPIO[11:10] are controlled by other internal signals 00533 #define X313_WA_CAMSYNCPER 0x7b // output sync period (32 bits, in pixel clocks). 0- stop. 1..256 - single, >=256 repetitive with specified period. 00534 #define SFPGA_TDI_BIT 0x0 00535 #define SFPGA_TMS_BIT 0x2 00536 #define SFPGA_TCK_BIT 0x4 00537 #define SFPGA_PROG_BIT 0x6 00538 #define SFPGA_PGMEN_BIT 0x8 00539 #define SFPGA_RD_SENSPGMPIN 0x80000 00540 #define SFPGA_RD_TDO 0x90000 00541 #define SFPGA_RD_DONE 0xa0000 00542 00543 00544 00545 //19:16 - 0xb..0xf - no changes 00546 // Mulptiplex status signals into a single line 00547 // - 0xa - select xfpgadone 00548 // - 0x9 - select xfpgatdo 00549 // - 0x8 - select senspgmin (default) 00550 // - 0x0..0x7 - no changes 00551 //15:10 - not used 00552 // 9: 8 - 3 - set xpgmen, 00553 // - 2 - reset xpgmen, 00554 // - 0, 1 - no changes to xpgmen 00555 // 7: 6 - 3 - set xfpgaprog, 00556 // - 2 - reset xfpgaprog, 00557 // - 0, 1 - no changes to xfpgaprog 00558 // 5: 4 - 3 - set xfpgatck, 00559 // - 2 - reset xfpgatck, 00560 // - 0, 1 - no changes to xfpgatck 00561 // 3: 2 - 3 - set xfpgatms, 00562 // - 2 - reset xfpgatms, 00563 // - 0, 1 - no changes to xfpgatms 00564 // 1: 0 - 3 - set xfpgatdi, 00565 // - 2 - reset xfpgatdi, 00566 // - 0, 1 - no changes to xfpgatdi 00567 00568 00569 // NOTE: Important note (issue came out with faster ETRAX FS). Due to write pipe and shared r/w addresses 00570 // it is not possible to read from registers 0x20.0x2f TWO cycles after any write to FPGA 00571 // The following dummy read will take 2 bus cycles 00572 #define X3X3_AFTERWRITE {if (!port_csp0_addr[X313__RA__MODEL]) printk ("model=0");} //just to be sure this read will not be optimized out 00573 #define x3x3_DELAY(x) {int iiii; for (iiii=0; iiii < (x); iiii++) X3X3_AFTERWRITE ; } 00574 00575 #define X313_WA_SDCH0_CTL0 0x20 // SDRAM control for Channel 0 - writing causes initialization of the channel 00576 //---353--- 00577 // 20 | | Channel 0 (16 bit data sensor->SDRAM) | Initialize channel: | (mode 0) | 00578 // | 31-16 | not used | 1) set address to startAddres | 31-30 | nbuf[1:0] | 00579 // | 15 | mode: 0 - 256x1 16-bit (or 512x1 bytes) | (word at address 01 with other | 29-18 | ntileY[11:0] | 00580 // | | 1 - 18x9 16 bit (or 18x18 bytes) | startAddress bits should be | 17-16 | ntileX[8:7] | 00581 // | | mode should be set to 0 for channel 0 | written earlier; | | | 00582 // | 14 | WnR - Write/not read. Should be 1 for channel 0 | 2) set nbuf[1:0] to 0 | 15-00 | Same as written | 00583 // | 13 | depend. Should be set to 1 if needed to synchronize | | | | 00584 // | | reading from SDRAM to writing from sensor | | | | 00585 // | 12-00 | frame start address startAddr[20:8]. Addressed are | | | | 00586 // | | 16-bit words, low 8 bits are 0 (aligned to 256 word | | | | 00587 // | | page boundary | | | | 00588 //---333--- 00589 // 20 | | Channel 0 (16 bit data sensor->SDRAM) | Initialize channel: | (mode 0) | 00590 // | 31-16 | not used | 1) set address to startAddres | 31-30 | nbuf[1:0] | 00591 // | 15 | mode: 0 - 256x1 16-bit (or 512x1 bytes) | (word at address 01 with other | 29-18 | ntileY[11:0] | 00592 // | | 1 - 18x9 16 bit (or 18x18 bytes) | startAddress bits should be | 17-16 | ntileX[8:7] | 00593 // | | mode should be set to 0 for channel 0 | written earlier; | | | 00594 // | 14 | WnR - Write/not read. Should be 1 for channel 0 | 2) set nbuf[1:0] to 0 | 15-00 | Same as written | 00595 // | 13 | depend. Should be set to 1 if needed to synchronize | | | | 00596 // | | reading from SDRAM to writing from sensor | | | | 00597 // | 12 | not used | | | | 00598 // | 11-00 | frame start address startAddr[19:8]. Addressed are | | | | 00599 // | | 16-bit words, low 8 bits are 0 (aligned to 256 word | | | | 00600 // | | page boundary | | | | 00601 //---313/323--- 00602 // 31-16 | not used | 1) set address to startAddres | 31 | nbuf (buffer page number) 00603 // 15 | mode: 0 - 128x1 16-bit (or 256x1 bytes) | (word at address 01 with other | | for ping-pong operation 00604 // | 1 - 16x8 16 bit (or 16x16 bytes) | startAddress bits should be | 30-19 | tileY (12 bits) if mode=0 00605 // | mode should be set to 0 for channel 0 | written earlier; | 18-16 | tileX ( 2 bits) if mode=0 00606 // 14 | WnR - Write/not read. Should be 1 for channel 0 | 2) set nbuf to 0 |READ 0x21 instead !!! 00607 // 13 | depend. Should be set to 1 if needed to synchronize | | 15-00 | Same as written 00608 // | reading from SDRAM to writing from sensor | 00609 // 12 | should be 0 | 00610 // 11-00 | frame start address startAddr[18:7]. Addressed are | 00611 // | 16-bit words, low 7 bits are 0 (aligned to 128 word | 00612 // | page boundary | 00613 #define X313_WA_SDCH0_CTL1 0x21 // | Channel 0 (16 bit data sensor->SDRAM) | none | 31 | nbuf (buffer page number) 00614 //---353--- 00615 // 21 | | Channel 0 (16 bit data sensor->SDRAM) | none | 31-30 | nbuf[1:0] | 00616 // | 31-14 | not used | | 29-18 | ntileY[11:0] | 00617 // | 13-04 | nTileX[9:0]. For mode=0 nTileX[9:5] specifies number| | 17 | 0 | 00618 // | | of the last 8x16 block to read in a line. | | 16 | ntileX[4] | 00619 // | | Actual number of 8x16 blocks in a line is nTileX+1 | | 15-00 | Same as written | 00620 // | | For mode0 last 128x16 may be partial if | | | | 00621 // | | nTileX[9:5] != 0x1F | | | | 00622 // | 03-00 | startAddr[24:21] - used with other bits specified | | | | 00623 // | | at address 20 | | | | 00624 //---333--- 00625 // 21 | | Channel 0 (16 bit data sensor->SDRAM) | none | 31-30 | nbuf[1:0] | 00626 // | 31-14 | not used | | 29-18 | ntileY[11:0] | 00627 // | 13-04 | nTileX[9:0]. For mode=0 nTileX[9:5] specifies number| | 17 | 0 | 00628 // | | of the last 8x16 block to read in a line. | | 16 | ntileX[4] | 00629 // | | Actual number of 8x16 blocks in a line is nTileX+1 | | 15-00 | Same as written | 00630 // | | For mode0 last 128x16 may be partial if | | | | 00631 // | | nTileX[9:5] != 0x1F | | | | 00632 // | 03-00 | startAddr[23:20] - used with other bits specified | | | | 00633 // | | at address 20 | | | | 00634 //---313/323--- 00635 // 31-13 | not used | | | for ping-pong operation 00636 // 12-04 | nTileX[8:0]. For mode=0 nTileX[8:4] specify number | | 30-19 | tileY (12 bits) if mode=0 00637 // | of the last 8x16 block to read in a line. | | 18-14 | tileX (4 bits) if mode=0 00638 // | Actual number of 8x16 blocks in a line is nTileX+1 | | | 00639 // | For mode0 last 128x16 may be partial if | | 13-00 | Same as written 00640 // | nTileX[3:0] != 0xF | | | 00641 // 03-00 | startAddr[22:19] - used with other bits specified | | | 00642 // | ar address 00 | | | 00643 #define X313_WA_SDCH0_CTL2 0x22 00644 //---333--- 00645 // 22 | | Channel 0 (16 bit data sensor->SDRAM) | none | 31-30 | nbuf[1:0] | 00646 // | 31-12 | not used | | 29-18 | ntileY[11:0] | 00647 // | 11-00 | nTileY[11:0] - (for mode=0) - number of the last | | 17 | 0 | 00648 // | | line in in a frame. Total number of lines in | | 16-12 | ntileX[4:0] | 00649 // | | a frame is nTileY[11:0]+1 (mode=0) or | | 11-00 | Same as written | 00650 // | | (nTileY[11:0] & 12'hff0)+18 if mode =1 | | | | 00651 // | | (nTileY >> 4) +1 of rows of 18x9x16 (18x18x8) tiles | | | | 00652 //---313/323--- 00653 // Channel 0 (16 bit data sensor->SDRAM) | none | 31-16 | same as for address=20 00654 // 31-11 | not used | | 15-00 | same as written 00655 // 10-00 | nTileY[10:0] - (for mode=0) - number of the last | | | 00656 // | line in in a frame. Total number of lines in | | | 00657 // | a frame is nTileY[10:0]+1 (mode=0) or | | | 00658 // | (nTileY[10:0] & 11'h7f0)+16 if mode =1 | | | 00659 // | (nTileY >> 4) +1 of rows of 16x8x16 (16x16x8) tiles | | | 00660 #define X313_WA_SD_MANCMD 0x23 00661 00662 // | Manual command to SDRAM for initialization. Works | Perform one-cycle SDRAM manual | 31-16 | same as for address=20 00663 // | (and is recommended) if SDRAM is disabled (see re- | command by driving | 15-00 | same as written 00664 // | gister 27) | RAS,CAS,WE,BA[1:0],A[11/12:0] | | 00665 //---333/353 --- 00666 // | 31-18 | not used | | | | 00667 // | 17 | RAS | | | | 00668 // | 16 | CAS | | | | 00669 // | 15 | WE | | | | 00670 // | 14-13 | bank address [1:0] | | | | 00671 // | 12-00 | address[12:0] | | | | 00672 //---313/323--- 00673 // 31-16 | not used | according to data bits | | 00674 // 15-14 | 00 - write mode reg (RAS=L, CAS=L, WE=L) | | | 00675 // | 01 - refresh (RAS=L, CAS=L, WE=H) | | | 00676 // | 10 - precharge (RAS=L, CAS=H, WE=L) | | | 00677 // | 11 - nop (RAS=H, CAS=H, WE=H) | | | 00678 // 13-12 | bank address [1:0] | | | 00679 // 11-00 | address[11:0] | | | 00680 #define X313_WA_SDCH1_CTL0 0x24 00681 //---333--- 00682 // 24 | | Channel 1 (16 bit FPN data from SDRAM) | Initialize channel: | 31 | nbuf (buffer page number) | 00683 // | 31-16 | not used | 1) set address to startAddres | | for ping-pong operation | 00684 // | 15 | mode: 0 - 128x1 16-bit (or 256x1 bytes) | (word at address 01 with other | 30-20 | tileY (11 bits) if mode=0 | 00685 // | | 1 - 16x8 16 bit (or 16x16 bytes) | startAddress bits should be | 19-16 | tileX ( 4 bits) if mode=0 | 00686 // | | mode should be set to 0 for channel 0 | written earlier; | | | 00687 // | 14 | WnR - Write/not read. Should be 0 for channel 1 | 2) set nbuf to 0 | 15-00 | Same as written | 00688 // | 13 | depend. Should be set to 0 as FPN data is supposed | 3) start reading SDRAM as WnR | | | 00689 // | | to be always ready. | is 0 if channel 1 is enabled | | | 00690 // | 12 | not used | | | | 00691 // | 11-00 | frame start address startAddr[18:7]. Addressed are | | | | 00692 // | | 16-bit words, low 7 bits are 0 (aligned to 128 word | | | | 00693 // | | page boundary | | | | 00694 //---313/323--- 00695 // | Channel 1 (16 bit FPN data from SDRAM) | Initialize channel: | 31 | nbuf (buffer page number) 00696 // 31-16 | not used | 1) set address to startAddres | | for ping-pong operation 00697 // 15 | mode: 0 - 128x1 16-bit (or 256x1 bytes) | (word at address 01 with other | 30-20 | tileY (11 bits) if mode=0 00698 // | 1 - 16x8 16 bit (or 16x16 bytes) | startAddress bits should be | 19-16 | tileX ( 4 bits) if mode=0 00699 // | mode should be set to 0 for channel 0 | written earlier; | | 00700 // 14 | WnR - Write/not read. Should be 0 for channel 1 | 2) set nbuf to 0 | 15-00 | Same as written 00701 // 13 | depend. Should be set to 0 as FPN data is supposed | 3) start reading SDRAM as WnR | | 00702 // | to be always ready. | is 0 if channel 1 is enabled | | 00703 // 12 | not used | | | 00704 // 11-00 | frame start address startAddr[18:7]. Addressed are | | | 00705 // | 16-bit words, low 7 bits are 0 (aligned to 128 word | | | 00706 // | page boundary | | | 00707 #define X313_WA_SDCH1_CTL1 0x25 00708 //---333--- 00709 // 25 | | Channel 1 (16 bit FPN data from SDRAM) | none | 31-16 | same as for address=24 | 00710 // | 31-14 | not used | | 15-00 | same as written | 00711 // | 13-04 | nTileX[6:0]. For mode=0 nTileX[6:4] specify number | | | | 00712 // | | of the last 8x16 block to read in a line. | | | | 00713 // | | Actual number of 8x16 blocks in a line is nTileX+1 | | | | 00714 // | | For mode0 last 128x16 may be partial if | | | | 00715 // | | nTileX[3:0] != 0xF | | | | 00716 // | 03-00 | startAddr[22:19] - used with other bits specified | | | | 00717 // | | ar address 24 | | | | 00718 //---313/323--- 00719 // | Channel 1 (16 bit FPN data from SDRAM) | none | 31-16 | same as for address=24 00720 // 31-13 | not used | | 15-00 | same as written 00721 // 12-04 | nTileX[8:0]. For mode=0 nTileX[8:4] specify number | | | 00722 // | of the last 8x16 block to read in a line. | | | 00723 // | Actual number of 8x16 blocks in a line is nTileX+1 | | | 00724 // | For mode0 last 128x16 may be partial if | | | 00725 // | nTileX[3:0] != 0xF | | | 00726 // 03-00 | startAddr[22:19] - used with other bits specified | | | 00727 // | ar address 00 | | | 00728 #define X313_WA_SDCH1_CTL2 0x26 00729 //---333--- 00730 // 26 | | Channel 1 (16 bit FPN data from SDRAM) | none | 31-16 | same as for address=24 | 00731 // | 31-11 | not used | | 15-00 | same as written | 00732 // | 10-00 | nTileY[10:0] - (for mode=0) - number of the last | | | | 00733 // | | line in in a frame. Total number of lines in | | | | 00734 // | | a frame is nTileY[10:0]+1 (mode=0) or | | | | 00735 // | | (nTileY[10:0] & 11'h7f0)+16 if mode =1 | | | | 00736 // | | (nTileY >> 4) +1 of rows of 16x8x16 (16x16x8) tiles | | | | 00737 //---313/323--- 00738 // | Channel 1 (16 bit FPN data from SDRAM) | none | 31-16 | same as for address=24 00739 // 31-11 | not used | | 15-00 | same as written 00740 // 10-00 | nTileY[10:0] - (for mode=0) - number of the last | | | 00741 // | line in in a frame. Total number of lines in | | | 00742 // | a frame is nTileY[10:0]+1 (mode=0) or | | | 00743 // | (nTileY[10:0] & 11'h7f0)+16 if mode =1 | | | 00744 // | (nTileY >> 4) +1 of rows of 16x8x16 (16x16x8) tiles | | | 00745 00746 // with ETRAX FS there was a problem reading this register right after write to 0x20..0x2f range 00747 #define X313_WA_SD_MODE 0x27 00751 //---333--- 00752 //same as 313/323 00753 //---313/323--- 00754 // | Set SDRAM operation mode | change SDRAM mode by enabling | 31-16 | same as for address=24 00755 // 31-06 | not used | channels specified in data | 15-00 | same as written 00756 // 05 | enXfer[3] - enable SDRAM transfers for Channel 3 | | | 00757 // | CPU <-> SDRAM through PIO | | | 00758 // 04 | enXfer[2] - enable SDRAM transfers for Channel 2 | | | 00759 // | SDRAM -> (compressor) -> CPU through DMA | | | 00760 // 03 | enXfer[1] - enable SDRAM transfers for Channel 1 | | | 00761 // | SDRAM-> sensor data processor (FPN correction) | | | 00762 // 02 | enXfer[0] - enable SDRAM transfers for Channel 0 | | | 00763 // | sensor ->(FPN correction) ->SDRAM | | | 00764 // 01 | enRefresh - enable SDRAM automatic refresh as a | | | 00765 // | background process | | | 00766 // 00 | enSDRAM - enable SDRAM controller. If set to 0 | | | 00767 // | only manual commands are allowed (see register | | | 00768 // | at address 03) | | | 00769 #define X313_WA_SDCH2_CTL0 0x28 00770 //---333--- 00771 // 28 | | Channel 2 (8 bit data to JPEG encoder or just DMA) | Initialize channel: | 31 | nbuf (buffer page number) | 00772 // | 31-16 | not used | 1) set address to startAddres | | for ping-pong operation | 00773 // | 15 | mode: 0 - 128x1 16-bit (or 256x1 bytes) - N/A | (word at address 01 with other | 30-20 | tileY (11 bits) if mode=0 | 00774 // | | 1 - 16x8 16 bit (or 16x16 bytes) ****** | startAddress bits should be | 19-16 | tileX ( 4 bits) if mode=0 | 00775 // | | mode maybe set to either 0 for sequential access | written earlier; | | | 00776 // | | to raw data, or to 1 for JPEG 18x18 MCU access | | 30-24 | tileY ( 7 bits) if mode=1 | 00777 // | 14 | WnR - Write/not read. Should be 0 for channel 2 | 2) set nbuf to 0 | 23-16 | tileX ( 8 bits) if mode=1 | 00778 // | 13 | depend. May be set to 1 to force encoder/DMA wait | 3) start reading SDRAM as WnR | | | 00779 // | | for sensor data available. Should work correctly | is 0 if channel 2 is enabled | 15-00 | Same as written | 00780 // | | for sequentional write and tiled read. | | | | 00781 // | 12 | not used | | | | 00782 // | 11-00 | frame start address startAddr[19:8]. Addressed are | | | | 00783 // | | 16-bit words, low 8 bits are 0 (aligned to 256 word | | | | 00784 // | | page boundary | | | | 00785 //---313/323--- 00786 // | Channel 2 (8 bit data to JPEG encoder or just DMA) | Initialize channel: | 31 | nbuf (buffer page number) 00787 // 31-16 | not used | 1) set address to startAddres | | for ping-pong operation 00788 // 15 | mode: 0 - 128x1 16-bit (or 256x1 bytes) | (word at address 01 with other | 30-20 | tileY (11 bits) if mode=0 00789 // | 1 - 16x8 16 bit (or 16x16 bytes) | startAddress bits should be | 19-16 | tileX ( 4 bits) if mode=0 00790 // | mode maybe set to either 0 for sequential access | written earlier; | | 00791 // | to raw data, or to 1 for JPEG 16x16 MCU access | | 30-24 | tileY ( 7 bits) if mode=1 00792 // 14 | WnR - Write/not read. Should be 0 for channel 2 | 2) set nbuf to 0 | 23-16 | tileX ( 8 bits) if mode=1 00793 // 13 | depend. May be set to 1 to force encoder/DMA wait | 3) start reading SDRAM as WnR | | 00794 // | for sensor data available. Should work correctly | is 0 if channel 2 is enabled | 15-00 | Same as written 00795 // | for sequentional write and tiled read. | | | 00796 // 12 | not used | | | 00797 // 11-00 | frame start address startAddr[18:7]. Addressed are | | | 00798 // | 16-bit words, low 7 bits are 0 (aligned to 128 word | | | 00799 // | page boundary | | | 00800 #define X313_WA_SDCH2_CTL1 0x29 00801 //---333--- 00802 // 29 | | Channel 2 (8 bit data to JPEG encoder or just DMA) | none | 31 | nbuf[1] | 00803 // | 31-14 | not used | | 30 | nbuf[0] | 00804 // | 13-04 | nTileX[9:0]. Mode is supposed to be 1 | | 29-22 | ntyleY[11:4] | 00805 // | | Actual number of 8x16 blocks in a line is nTileX+1 | | 21-16 | ntileX[9:4] | 00806 // | | | | | | 00807 // | 03-00 | startAddr[23:20] - used with other bits specified | | | | 00808 // | | at address 28 | | | | 00809 //---313/323--- 00810 // | Channel 2 (8 bit data to JPEG encoder or just DMA) | none | 31-16 | same as for address=28 00811 // 31-13 | not used | | 15-00 | same as written 00812 // 12-04 | nTileX[8:0]. For mode=0 nTileX[8:4] specify number | | | 00813 // | of the last 8x16 block to read in a line. | | | 00814 // | Actual number of 8x16 blocks in a line is nTileX+1 | | | 00815 // | For mode0 last 128x16 may be partial if | | | 00816 // | nTileX[3:0] != 0xF | | | 00817 // 03-00 | startAddr[22:19] - used with other bits specified | | | 00818 // | ar address 00 | | | 00819 #define X313_WA_SDCH2_CTL2 0x2a 00820 //---333--- 00821 // 2a | | Channel 2 (8 bit data to JPEG encoder or just DMA) | none | 31 | nbuf[1] | 00822 // | 31-12 | not used | | 30 | nbuf[0] | 00823 // | 11-00 | nTileY[11:0] - (for mode=0) - number of the last | | 29-22 | ntyleY[11:4] | 00824 // | | line in in a frame. Total number of lines in | | 21-12 | ntileX[9:0] | 00825 // | | a frame is nTileY[10:0]+1 (mode=0) or | | 11-00 | Same as written | 00826 // | | (nTileY[10:0] & 11'h7f0)+16 if mode =1 | | | | 00827 // | | (nTileY >> 4) +1 of rows of 16x8x16 (16x16x8) tiles | | | | 00828 //---313/323--- 00829 // | Channel 2 (8 bit data to JPEG encoder or just DMA) | none | 31-16 | same as for address=28 00830 // 31-11 | not used | | 15-00 | same as written 00831 // 10-00 | nTileY[10:0] - (for mode=0) - number of the last | | | 00832 // | line in in a frame. Total number of lines in | | | 00833 // | a frame is nTileY[10:0]+1 (mode=0) or | | | 00834 // | (nTileY[10:0] & 11'h7f0)+16 if mode =1 | | | 00835 // | (nTileY >> 4) +1 of rows of 16x8x16 (16x16x8) tiles | | | 00836 #define X313_WA_SDCH3_CTL0 0x2c 00837 //---333--- 00838 // 2c | | Channel 3 (CPU PIO <-> SDRAM) | Initialize channel: | (mode 0) | 00839 // | 31-16 | not used | 1) set address to startAddres | 31-30 | nbuf[1:0] | 00840 // | 15 | mode: 0 - 256x1 16-bit (or 512x1 bytes) | (word at address 01 with other | 29-18 | ntileY[11:0] | 00841 // | | 1 - 18x9 16 bit (or 18x18 bytes) | startAddress bits should be | 17-16 | ntileX[8:7] | 00842 // | | mode should be set to 0 for channel 0 | written earlier; | | | 00843 // | 14 | WnR - Write/not read. Should be 1 for channel 0 | 2) set nbuf[1:0] to 0 | 15-00 | Same as written | 00844 // | 13 | depend. Should be set to 1 if needed to synchronize | | | | 00845 // | | reading from SDRAM to writing from sensor | | | | 00846 // | 12 | not used | | | | 00847 // | 11-00 | frame start address startAddr[19:8]. Addressed are | | | | 00848 // | | 16-bit words, low 8 bits are 0 (aligned to 256 word | | | | 00849 // | | page boundary | | | | 00850 //---313/323--- 00851 // | Channel 3 (CPU PIO <-> SDRAM) | Initialize channel: | 31 | nbuf (buffer page number) 00852 // 31-16 | not used | 1) set address to startAddres | | for ping-pong operation 00853 // 15 | mode: 0 - 128x1 16-bit (or 256x1 bytes) | (word at address 01 with other | 30-20 | tileY (11 bits) if mode=0 00854 // | 1 - 16x8 16 bit (or 16x16 bytes) | startAddress bits should be | 19-16 | tileX ( 4 bits) if mode=0 00855 // | mode maybe set to either 0 for sequential access | written earlier; | | 00856 // | to raw data, or to 1 16x16x8 tiled | | 30-24 | tileY ( 7 bits) if mode=1 00857 // 14 | WnR - Write/not read. May be set to any value for | 2) set nbuf to 0 | 23-16 | tileX ( 8 bits) if mode=1 00858 // | Channel 3 - it works both ways | | | 00859 // 13 | depend. May be set to 1 to force the channel wait | 3) start reading SDRAM if WnR | | 00860 // | for sensor data available. (Read through status) | is 0 and channel 3 is enabled | 15-00 | Same as written 00861 // 12 | read DC coimponents instead of SDRAM | | | 00862 // 11-00 | frame start address startAddr[18:7]. Addressed are | | | 00863 // | 16-bit words, low 7 bits are 0 (aligned to 128 word | | | 00864 // | page boundary | | | 00865 #define X313_WA_SDCH3_CTL1 0x2d 00866 //---333--- 00867 // 2d | | Channel 3 (CPU PIO <-> SDRAM) | none | 31-30 | nbuf[1:0] | 00868 // | 31-14 | not used | | 29-18 | ntileY[11:0] | 00869 // | 13-04 | nTileX[9:0]. For mode=0 nTileX[9:5] specifies number| | 17 | 0 | 00870 // | | of the 8x16 blocks to read in a line. | | 16 | ntileX[4] | 00871 // | | Actual number of 8x16 blocks in a line is nTileX+1 | | 15-00 | Same as written | 00872 // | | For mode0 last 256x16 may be partial if | | | | 00873 // | | nTileX[9:5] != 0x00 | | | | 00874 // | 03-00 | startAddr[23:20] - used with other bits specified | | | | 00875 // | | at address 2c | | | | 00876 //---313/323--- 00877 // | Channel 3 (CPU PIO <-> SDRAM) | none | 31-16 | same as for address=2c 00878 // 31-13 | not used | | 15-00 | same as written 00879 // 12-04 | nTileX[8:0]. For mode=0 nTileX[8:4] specify number | | | 00880 // | of the last 8x16 block to read in a line. | | | 00881 // | Actual number of 8x16 blocks in a line is nTileX+1 | | | 00882 // | For mode0 last 128x16 may be partial if | | | 00883 // | nTileX[3:0] != 0xF | | | 00884 // 03-00 | startAddr[22:19] - used with other bits specified | | | 00885 // | ar address 00 | | | 00886 #define X313_WA_SDCH3_CTL2 0x2e 00887 //---333--- 00888 // 2e | | Channel 3 (CPU PIO <-> SDRAM) | none | 31-30 | nbuf[1:0] | 00889 // | 31-12 | not used | | 29-18 | ntileY[11:0] | 00890 // | 11-00 | nTileY[11:0] - (for mode=0) - number of the last | | 17 | 0 | 00891 // | | line in in a frame. Total number of lines in | | 16-12 | ntileX[4:0] | 00892 // | | a frame is nTileY[11:0]+1 (mode=0) or | | 11-00 | Same as written | 00893 // | | (nTileY[11:0] & 12'hff0)+18 if mode =1 | | | | 00894 // | | (nTileY >> 4) +1 of rows of 18x9x16 (18x18x8) tiles | | | | 00895 //---313/323--- 00896 // | Channel 3 (CPU PIO <-> SDRAM) | none | 31-16 | same as for address=2c 00897 // 31-11 | not used | | 15-00 | same as written 00898 // 10-00 | nTileY[10:0] - (for mode=0) - number of the last | | | 00899 // | line in in a frame. Total number of lines in | | | 00900 // | a frame is nTileY[10:0]+1 (mode=0) or | | | 00901 // | (nTileY[10:0] & 11'h7f0)+16 if mode =1 | | | 00902 // | (nTileY >> 4) +1 of rows of 16x8x16 (16x16x8) tiles | | | 00903 #define X313_WA_SDPIO_NEXT 0x2f 00904 //---333--- 00905 // similar to 313/333 but will open access to next 128x32bit page, resets address inside page 00906 //---313/323--- 00907 // | Channel 3 (CPU PIO <-> SDRAM) | Next page (8x32 bit window) | 31-16 | same as for address=2c 00908 // 31-00 | not used | for CPU PIO access. Check | 15-00 | same as written 00909 // | | status bit to see ifbuffer is | | 00910 // | | ready | | 00911 #define X313_WA_SD_PIOWIN 0x30 00912 00913 #define X313_WA_LENSCORR 0x31 00914 00915 #define X313_LENS_AX(x) ( 0x0 | ((x)& 0x7ffff)) 00916 #define X313_LENS_AY(x) ( 0x80000 | ((x)& 0x7ffff)) 00917 #define X313_LENS_C(x) (0x100000 | ((x)& 0x7ffff)) 00918 #define X313_LENS_BX(x) (0x200000 | ((x)& 0x1fffff)) 00919 #define X313_LENS_BY(x) (0x400000 | ((x)& 0x1fffff)) 00920 #define X313_LENS_SCALES(color,x) (0x600000 | (((color)&3)<<17) | ((x)& 0x1ffff)) 00921 #define X313_LENS_FATZERO_IN(x) (0x680000 | ((x)& 0xffff)) 00922 #define X313_LENS_FATZERO_OUT(x) (0x690000 | ((x)& 0xffff)) 00923 #define X313_LENS_POSTSCALE(x) (0x6a0000 | ((x)& 0x7)) 00924 00925 00926 /*!******************************************************************************************************* 00927 *! Moved all references to FPGA access to memory-control registers here to simplify code maitenance 00928 *! when FPGA changes. 00929 *! 00930 *! Split SDARM channel initailization in 3 macros 00931 *! X313_PREINIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) - writes two (of 3) registers (not yet starting the channel) 00932 *! returns value foo the 3-rd (command) register 00933 *! X313_PREINIT_SDCHAN(num,cmd) - writes the channel command register, starting it 00934 *! waits 2 cycles after (if ETRAX FS) to make next reads safe 00935 *! X313_INIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) - combination of the 2 above, works as before 00936 *! 00937 *!/ added X3X3_AFTERWRITE to be able to read FPGA after that macro (w/o -= failed in ETRAX FS) 00938 */ 00939 00940 #define RD_SD_PIOWIN port_csp4_addr[X313_WA_SD_PIOWIN] 00941 00943 #define X313_PREINIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) \ 00944 ((port_csp0_addr[X313_WA_SDCH0_CTL0+1+((num)<<2)] = (0x8000 | (((ntilex) & 0x3ff) << 4) | (((sa) >> 21) & 0xf))), \ 00945 (port_csp0_addr[X313_WA_SDCH0_CTL0+2+((num)<<2)] = ((ntiley) & 0xfff)), \ 00946 (((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 8) & 0x1fff)) 00947 #define X313_POSTINIT_SDCHAN(num,cmd) {port_csp0_addr[X313_WA_SDCH0_CTL0+0+((num)<<2)] = cmd; X3X3_AFTERWRITE} 00948 #define X313_INIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) \ 00949 {X313_POSTINIT_SDCHAN ( num, X313_PREINIT_SDCHAN ( num,mode,wnr,dep,sa,ntilex,ntiley ))} 00950 00952 #define X313_SDCHAN_REG0(mode,wnr,dep,sa,ntilex,ntiley) ((((mode) & 1) << 15) | (((wnr) & 1) << 14) | (((dep) & 1) << 13) | (((sa) >> 8) & 0x1fff)) 00953 #define X313_SDCHAN_REG1(mode,wnr,dep,sa,ntilex,ntiley) (0x8000 | (((ntilex) & 0x3ff) << 4) | (((sa) >> 21) & 0xf)) 00954 #define X313_SDCHAN_REG2(mode,wnr,dep,sa,ntilex,ntiley) ((ntiley) & 0xfff) 00956 00957 00958 #define X313_CHN_EN_D(x) ((0x30 << (((x)& 3)<<1)) | 0xf) // enable selected channel (and memory+refresh, just in case too) 00959 #define X313_CHN_DIS_D(x) (0x20 << (((x)& 3)<<1)) // disable selected channel 00960 #define X313_CHN_DISALL_D 0xaa0 // disable all channels, do not modify refresh or memory as a whole 00961 #define X313_SDRAM_OFF_D 0xaaa // disable all chennels, refresh and memory itself 00962 #define X313_SDRAM_ON_D 0xaaf // will disable all channels but refresh 00963 00964 #define X313_CHN_EN(x) {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_EN_D(x); } // added | 0xf so SDRAM will be enabled too 00965 #define X313_CHN_DIS(x) {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_DIS_D(x); } 00966 #define X313_CHN_DISALL {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] = X313_CHN_DISALL_D ; } 00967 #define X313_SDRAM_OFF {port_csp0_addr[X313_WA_SD_MODE]= X313_SDRAM_OFF_D;} // no need to wait here 00968 #define X313_SDRAM_ON {port_csp0_addr[X313_WA_SD_MODE]= X313_SDRAM_ON_D;} // no need to wait here - will disable all channels but refresh 00969 00970 #define X313_IS_SDRAM_ON (port_csp0_addr[X313_WA_SD_MODE],((port_csp0_addr[X313_WA_SD_MODE] & 3)==3)) // first - dummy read 00971 #define X313_CHN0_BOUND (port_csp0_addr[X313_WA_SDCH2_CTL0],(port_csp0_addr[X313_WA_SDCH2_CTL0] & 0x2000)) 00972 00973 #define X313_XFERCNTR (port_csp0_addr[X313__RA__XFERCNTR],port_csp0_addr[X313__RA__XFERCNTR]) 00974 #define X313_HIGHFREQ (port_csp0_addr[X313__RA__HIGHFREQ],port_csp0_addr[X313__RA__HIGHFREQ]) 00975 #define X313_IRQSTATE (port_csp0_addr[0x11],port_csp0_addr[0x11]) 00976 #define X313_IOPINS (port_csp0_addr[X313__RA__IOPINS],port_csp0_addr[X313__RA__IOPINS]) 00977 00979 #define X313_CHN0_USED ( (port_csp0_addr[X313_WA_SDCH0_CTL1]& 0xffff), \ 00980 (port_csp0_addr[X313_WA_SDCH0_CTL1] & 0xffff) ) 00981 00982 #define X313_CHN0_SET_USED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0x8000; } 00983 #define X313_CHN0_SET_UNUSED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0; } 00984 00985 00986 #define X313_SET_FPGA_TIME(x,y) { port_csp0_addr[X313_WA_RTC_USEC]= ( y ); port_csp0_addr[X313_WA_RTC_SEC]= ( x ); } 00987 #define X313_GET_FPGA_TIME(x,y) { port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]; y = port_csp0_addr[X313_WA_RTC_USEC];} 00988 #define X313_GET_FPGA_SECONDS(x) { port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]} 00989 00990 00991 00992 // As I will use application, not driver to access frame memory, I'll put here SDRAM memory map 00993 // The window size is designed to fit 1280x1024x16 - FPN, twice as much for image 00994 #define X313_MAP_FPN 0 00995 #define X313_SDRAM_SIZE 0x4000000 00996 #define X313_MAXWIDTH 4096 // multiple of 128 00997 #define X313_MAXHEIGHT 4096 // multiple of 16 (actual - 2720) 00998 #define X313_MAP_FRAME ((X313_MAP_FPN) + (X313_MAXWIDTH) * (X313_MAXHEIGHT)) 00999 #define X313_MARGINS 4 01000 #define X313_TILEHOR 16 01001 #define X313_TILEVERT 16
1.5.1