os/linux-2.6-tag--devboard-R2_10-4/arch/cris/arch-v32/drivers/elphel/fpgactrl353.c

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/*!***************************************************************************
*! FILE NAME  : fpgactrl353.c
*! DESCRIPTION: Provides sensor-independent access to FPGA in Elphel mModel 353 camera
*! Includes I/O for the dedicated (to FPGA) DDR SDRAM
*! Copyright 2002-2007 (C) Elphel, Inc.
*! -----------------------------------------------------------------------------**
*!
*!  This program is free software: you can redistribute it and/or modify
*!  it under the terms of the GNU General Public License as published by
*!  the Free Software Foundation, either version 3 of the License, or
*!  (at your option) any later version.
*!
*!  This program is distributed in the hope that it will be useful,
*!  but WITHOUT ANY WARRANTY; without even the implied warranty of
*!  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*!  GNU General Public License for more details.
*!
*!  You should have received a copy of the GNU General Public License
*!  along with this program.  If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!  $Log: fpgactrl353.c,v $
*!  Revision 1.1.1.1  2008/11/27 20:04:00  elphel
*!
*!
*!  Revision 1.5  2008/09/22 22:55:48  elphel
*!  snapshot
*!
*!  Revision 1.4  2008/09/20 00:29:50  elphel
*!  moved driver major/minor numbers to a single file - include/asm-cris/elphel/driver_numbers.h
*!
*!  Revision 1.3  2008/09/16 00:49:30  elphel
*!  snapshot
*!
*!  Revision 1.2  2008/09/12 00:23:59  elphel
*!  removed cc353.c, cc353.h
*!
*!  Revision 1.1.1.1  2007/08/17 10:23:18  elphel
*!  This is a fresh tree based on elphel353-2.10
*!
*!  Revision 1.7  2007/08/17 10:23:18  spectr_rain
*!  switch to GPL3 license
*!
*!  Revision 1.6  2007/07/20 10:17:46  spectr_rain
*!  *** empty log message ***
*!
*!  Revision 1.2  2007/05/21 17:45:10  elphel
*!  boundary scan support, added 359/347 detection
*!
*!  Revision 1.1.1.1  2007/02/23 10:11:48  elphel
*!  initial import into CVS
*!
*!  Revision 1.2  2005/05/10 21:08:49  elphel
*!  *** empty log message ***
*!
*/
/****************** INCLUDE FILES SECTION ***********************************/


#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/autoconf.h>

#include <asm/system.h>
#include <asm/arch/memmap.h>

//#include <asm/svinto.h>
#include <asm/io.h>

#include <asm/irq.h>

#include <asm/delay.h>
#include <asm/uaccess.h>
#include <asm/elphel/driver_numbers.h>
#include <asm/elphel/fpgaconfa.h>
#include <asm/elphel/c313a.h> // just for ELPHEL_DEBUG

#include "fpgactrl.h"
#include "fpga_io.h"
#include "fpga_sdram.h"
#include "x3x3.h"
#define ELPHEL_DEBUG_THIS 0
#if ELPHEL_DEBUG_THIS
//#if ELPHEL_DEBUG
  #define D1(x) x
  #define MD1(x) printk("%s:%d:",__FILE__,__LINE__);x
  #define MDD1(x) printk("%s:%d:",__FILE__,__LINE__); x ; udelay (ELPHEL_DEBUG_DELAY)
  #define D1I(x)
#else
  #define D1(x)
//  #define MD1(x) printk("%s:%d:",__FILE__,__LINE__);x
  #define MD1(x)
  #define MDD1(x)
  #define D1I(x) x
#endif


#define FPGA_MODULE_DESCRIPTION "FPGA control driver for Elphel (R) Model 353 camera"
#define FPGA_DRIVER_NAME "fpga_control"
#define FPGA_MAXMINOR 10

//extern volatile unsigned long ccam_cr_shadow;

static const char fpga_name[] = "fpga_control";
static int minors[FPGA_MAXMINOR+1];     // each minor can be opened only once
static int     fpga_open   (struct inode *inode, struct file *filp);
static int     fpga_release(struct inode *inode, struct file *filp);
static int     fpga_ioctl  (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg);
static ssize_t fpga_write  (struct file * file, const char * buf, size_t count, loff_t *off);
static loff_t  fpga_lseek  (struct file * file, loff_t offset, int orig);
static ssize_t fpga_read   (struct file * file, char * buf, size_t count, loff_t *off);

//static loff_t fpga_lseek(struct file * file, loff_t offset, int orig);
//static ssize_t fpga_read(struct file * file, char * buf, size_t count, loff_t *off);

//static int __init fpga_init(void);

static struct file_operations fpga_fops = {
        owner:    THIS_MODULE,
        open:     fpga_open,
        release:  fpga_release,
        ioctl:    fpga_ioctl,
        llseek:   fpga_lseek,
        read:     fpga_read,
        write:    fpga_write
};

/* ======================================== Top level file operations =================================================================== */
static int fpga_open(struct inode *inode, struct file *filp) {
        int p;
        int res;

        p = MINOR(inode->i_rdev);
     D1(printk("fpga_open: minor=%x\r\n",p) );
     D1(printk("filp=%lx\r\n",(unsigned long)filp) );

        switch ( p ) {
        case FPGACONF_MINOR_SDRAM : {
              if (minors[p])  return -EACCES;
// is fpga loaded?
     MD1(printk("fpga_open: fpga_state=0x%x\n",(int) fpga_state) );
          if ((fpga_state & FPGA_STATE_LOADED) ==     0) return -EACCES; // change to particular fpga revision
          if ((fpga_state & FPGA_STATE_CLOCKS) ==     0) return -EACCES; // clocks not running
          if (((fpga_state & FPGA_STATE_SDRAM_INIT) == 0)  || (!X313_IS_SDRAM_ON))fpga_initSDRAM();

     MD1(printk("fpga_open: fpga_state=0x%x\n",(int) fpga_state) );
          if ((res=fsdram_open(inode, filp))<0)return res;
          break;
        }
        case FPGACONF_MINOR_IORW :
        case FPGACONF_MINOR_TABLES:
          {
            if (minors[p])  return -EACCES;
            break;
          }
        default: return -EINVAL;
        }
        minors[p]=p;

        filp->private_data = &minors[p];
        return 0;
}

static int fpga_release(struct inode *inode, struct file *filp) {
   int res=0;
   int p = MINOR(inode->i_rdev);
   switch ( p ) {
     case FPGACONF_MINOR_SDRAM :
       res= fsdram_release();
       minors[p]=0;
       return res;
     case FPGACONF_MINOR_IORW :
     case FPGACONF_MINOR_TABLES:
       minors[p]=0;
       break;
     default: return -EINVAL;
   }
  D1(printk("fpga_release:  done\r\n"));
  return 0;
}



static int fpga_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { // switch by minor
//   int res=0;
   D1(printk("fpga_ioctl cmd= %x, arg= %x\n\r",cmd,(int) arg));

   switch (((int *)filp->private_data)[0]) {
      case FPGACONF_MINOR_IORW : {// read write FPGA registers
        D1(printk("fpga_ioctl cmd= %x, arg= %x\n\r",cmd,(int) arg));
        if(_IOC_TYPE(cmd) == FPGACONF_GETSTATE) {
            return fpga_state;
        }
        return fpga_io_ioctl (inode, filp, cmd, arg);
      }
      default:return -EINVAL;
   }
}



static ssize_t fpga_write(struct file * file, const char * buf, size_t count, loff_t *off) {
    D1(printk("fpga_write: ((int *)file->private_data)[0]= %x\r\n",((int *)file->private_data)[0]));
    switch (((int *)file->private_data)[0]) {
       case FPGACONF_MINOR_IORW :  return fpga_io_write      (file, buf, count, off);
       case FPGACONF_MINOR_SDRAM : return fsdram_write       (file, buf, count, off);
       case FPGACONF_MINOR_TABLES: return fpga_io_table_write(file, buf, count, off);
       default:                 return -EINVAL;
    }
}

static loff_t  fpga_lseek(struct file * file, loff_t offset, int orig) {
    D1(printk (" file=%x, offset=%x, orig=%x\r\n", (int) file, (int) offset, (int) orig));
     switch (((int *)file->private_data)[0]) {
       case FPGACONF_MINOR_IORW :   return fpga_io_lseek       (file, offset, orig);
       case FPGACONF_MINOR_SDRAM :  return fsdram_lseek        (file, offset, orig);
       case FPGACONF_MINOR_TABLES:  return fpga_io_table_lseek (file, offset, orig);
       default:                 return -EINVAL;
    }
}

static ssize_t fpga_read(struct file * file, char * buf, size_t count, loff_t *off) {
    switch (((int *)file->private_data)[0]) {
       case FPGACONF_MINOR_IORW :   return fpga_io_read(file, buf, count, off);
       case FPGACONF_MINOR_SDRAM :      return fsdram_read(file, buf, count, off);
       default:                 return -EINVAL;
    }
}




void init_elphel_ioremap(void) {
// Do not need to iounmap as these addersses will stay on with the camera
        port_csp0_addr = ioremap(MEM_CSR0_START | MEM_NON_CACHEABLE, 8192);
        port_csp4_addr = ioremap(MEM_CSP4_START | MEM_NON_CACHEABLE, 8192);
        if (!port_csp0_addr || !port_csp0_addr) {
                printk(FPGA_MODULE_DESCRIPTION" failed to ioremap\n");
// panic here?
        }
}


static int __init 
fpga_init(void)
{
        init_elphel_ioremap(); // map address ranges to use port0 and port4 in FPGA accesses.
        int i,res;
        res = register_chrdev(FPGA_MAJOR, fpga_name, &fpga_fops);
        if(res < 0) {
                printk(KERN_ERR "\nfpga_init: couldn't get a major number  %d.\n ",FPGA_MAJOR);
                return res;
        }
        printk(FPGA_DRIVER_NAME"- %d\n",FPGA_MAJOR);


        for (i=0;i<=FPGA_MAXMINOR;i++) minors[i]=0;
        fpga_state=0;    // bit 0 - FPGA state, 1 - Clocks, 2 - SDRAM
//        printk("FPGA is not loaded, clocks are not programmed, SDRAM is not initialized\r\n");
        return 0;
}



/* this makes sure that fpga_init is called during boot */

module_init(fpga_init);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Andrey Filippov <andrey@elphel.com>.");
MODULE_DESCRIPTION(FPGA_MODULE_DESCRIPTION);

---