x393
1.0
FPGAcodeforElphelNC393camera
table_ad_transmit.v
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1
41
`timescale 1ns/1ps
42
43
module
table_ad_transmit
#(
44
parameter
NUM_CHANNELS
=
1
,
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parameter
ADDR_BITS
=
4
46
)(
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input
clk
,
// posedge mclk
48
input
srst
,
// reset @posedge clk
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input
a_not_d_in
,
// address/not data input (valid @ we)
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input
we
,
// write address/data (single cycle) with at least 5 inactive between
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input
[
31
:
0
]
din
,
// 32 bit data to send or 8-bit channel select concatenated with 24-bit byte address (@we)
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output
[
7
:
0
]
ser_d
,
// 8-bit address/data to be sent to submodules that have table write port(s), LSB first
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output
reg
a_not_d
,
// sending adderass / not data - valid during all bytes
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output
reg
[
NUM_CHANNELS
-
1
:
0
]
chn_en
// sending address or data
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);
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wire
[
NUM_CHANNELS
-
1
:
0
]
sel
;
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reg
[
31
:
0
]
d_r
;
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reg
any_en
;
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reg
[
ADDR_BITS
-
1
:
0
]
sel_a
;
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reg
we_r
;
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wire
we3
;
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assign
ser_d
=
d_r
[
7
:
0
];
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always
@ (
posedge
clk
)
begin
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if
(
we
)
d_r
<=
din
;
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else
if
(
any_en
)
d_r
<=
d_r
>>
8
;
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if
(
we
)
a_not_d
<=
a_not_d_in
;
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we_r
<=
we
&&
a_not_d_in
;
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if
(
srst
)
any_en
<=
0
;
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else
if
((
we
&& !
a_not_d_in
) ||
we_r
)
any_en
<=
1
;
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else
if
(
we3
)
any_en
<=
0
;
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if
(
srst
)
chn_en
<=
0
;
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else
if
((
we
&& !
a_not_d_in
) ||
we_r
)
chn_en
<=
sel
;
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else
if
(
we3
)
chn_en
<=
0
;
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if
(
we
&&
a_not_d_in
)
sel_a
<=
din
[
24
+:
ADDR_BITS
];
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end
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// dly_16 #(.WIDTH(1)) i_end_burst(.clk(clk),.rst(1'b0), .dly(4'd2), .din(we), .dout(we3)); // dly=2+1=3
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dly_16
#(.
WIDTH
(
1
))
i_end_burst
(.
clk
(
clk
),.
rst
(
1'b0
), .
dly
(
4'd3
), .
din
(
we
), .
dout
(
we3
));
// dly=3+1=4
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genvar
i
;
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generate
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for
(
i
=
0
;
i
<
NUM_CHANNELS
;
i
=
i
+
1
)
begin
:
gsel
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assign
sel
[
i
] =
sel_a
==
i
;
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end
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endgenerate
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endmodule
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dly_16.10332clk
10332clk
Definition:
dly_16.v:44
table_ad_transmit.11073we3
11073we3wire
Definition:
table_ad_transmit.v:61
table_ad_transmit
Definition:
table_ad_transmit.v:43
table_ad_transmit.11072we_r
11072we_rreg
Definition:
table_ad_transmit.v:60
table_ad_transmit.11069d_r
11069d_rreg[31:0]
Definition:
table_ad_transmit.v:57
table_ad_transmit.11068sel
11068selwire[NUM_CHANNELS-1:0]
Definition:
table_ad_transmit.v:56
table_ad_transmit.11061srst
11061srst
Definition:
table_ad_transmit.v:48
table_ad_transmit.11071sel_a
11071sel_areg[ADDR_BITS-1:0]
Definition:
table_ad_transmit.v:59
table_ad_transmit.11062a_not_d_in
11062a_not_d_in
Definition:
table_ad_transmit.v:49
dly_16.10336dout
[WIDTH-1:0] 10336dout
Definition:
dly_16.v:48
table_ad_transmit.11064din
[31:0] 11064din
Definition:
table_ad_transmit.v:51
table_ad_transmit.11066a_not_d
reg 11066a_not_d
Definition:
table_ad_transmit.v:53
dly_16.10335din
[WIDTH-1:0] 10335din
Definition:
dly_16.v:47
table_ad_transmit.dly_16
i_end_burst dly_16
Definition:
table_ad_transmit.v:85
table_ad_transmit.11058NUM_CHANNELS
11058NUM_CHANNELS1
Definition:
table_ad_transmit.v:44
table_ad_transmit.11060clk
11060clk
Definition:
table_ad_transmit.v:47
table_ad_transmit.11067chn_en
reg [NUM_CHANNELS-1:0] 11067chn_en
Definition:
table_ad_transmit.v:54
table_ad_transmit.11059ADDR_BITS
11059ADDR_BITS4
Definition:
table_ad_transmit.v:45
dly_16.10333rst
10333rst
Definition:
dly_16.v:45
table_ad_transmit.11070any_en
11070any_enreg
Definition:
table_ad_transmit.v:58
table_ad_transmit.11063we
11063we
Definition:
table_ad_transmit.v:50
table_ad_transmit.11065ser_d
[ 7:0] 11065ser_d
Definition:
table_ad_transmit.v:52
dly_16.10334dly
[3:0] 10334dly
Definition:
dly_16.v:46
util_modules
table_ad_transmit.v
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