51 parameter SENSI2C_TBL_NABRD =
19,
// number of address bytes for read (0 - 1 byte, 1 - 2 bytes) 52 parameter SENSI2C_TBL_DLY =
20,
// bit delay (number of mclk periods in 1/4 of SCL period) 55 input mrst,
// @ posedge mclk 56 input mclk,
// global clock 60 input early_release_0,
// global config bit: release SDA immediately after end of SCL if next bit is 1 (for ACKN). Data hold time by slow 0->1 61 // setup LUT to translate address page into SA, actual address MSB and number of bytes to write (second word bypasses translation) 62 input tand,
// table address/not data 63 input [
27:
0]
td,
// table address/data in 64 input twe,
// table write enable 69 output reg i2c_run,
// released as soon as the last command (usually STOP) gets to the i2c start/stop/shift module 70 output reg i2c_busy,
// released when !i2c_run and all i2c activity is over 71 output reg [
1:
0]
seq_mem_ra,
// number of byte to read from the sequencer memory 72 output [
1:
0]
seq_mem_re,
// [0] - re, [1] - regen to the sequencer memory 73 input [
7:
0]
seq_rd,
// data from the sequencer memory 78 Sequencer provides 4 bytes per command, read one byte at a time as seq_rd[7:0] with byte address provided by seq_mem_ra[1:0], 79 seq_mem_re[0] external memory re, seq_mem_re[1] - regen 80 MSB (byte 3) is used as index in the table that provides for register writes (tdout[8] == 0): 81 high byte of the register address (if used) - tdout[7:0] 82 slave address - tdout[15:9], 83 number of bytes to send after SA - tdout[19:16] (includes both adderss and data bytes, aligned to the MSB) 84 bit delay - tdout[27:20] (periods of mclk for 1/4 of the SCL period), should be >2(?) 86 if number of bytes to send (including address) >4, there will be no stop and the next command will bypass MSB decoding through table 87 and be sent out as data bytes (MSB first, aligned to the LSB (byte[0]), so if only one byte is to be sent bytes[3:1] will be skipped. 88 In read mode (tdout[8] == 1) it is possible to use 1 or 2 byte register address and read 1..8 bytes 89 bit delay - tdout[27:20] (same as for register writes - see above) 90 Slave address in the read mode is provided as byte[2], register adderss in bytes[1:0] (byte[1] is skipped for 1-byte addresses) 91 Number of data bytes to read is provided as tdout[18:16], with 0 meaning 8 bytes 92 Nuber of register address bytes is defined by tdout[19]: 0 - one byte, 1 - 2 bytes address 93 "active_sda" (configuration bit enables active pull-up on SDA line by the master for faster communication, it is active during second 94 half of the SCL=0 for the data bits and also for the first interval of the RESTART sequence and for the last of the STOP one. 95 "early_release_0" - when sending data bit "0" over the SDA line, release SDA=0 immediately after SCL: 1->0 if the next bit to send is "1". 96 This is OK as the SDA 0->1 transition will be slower than SCL 1->0 (only pulled up by a resistor), so there will be positive hold time 97 on SDA line. This is done so for communications with 10359 (or similar) board where FPGA can also actively drive SDA line for faster 99 Active driving of the SDA line increases only master send communication, so ACKN may be missed, but it is not used in this implementation. 100 Reading registers is less used operation than write and can use slower communication spped (provided through the table) 104 reg [
7:
0]
reg_ah;
// MSB of the register address (instead of the byte 2) 105 reg [
7:
0]
slave_a_rah;
// 8-bit slave address , used instead of the byte 3, later replaced with reg_ah 106 reg [
3:
0]
num_bytes_send;
// number of bytes to send (if more than 4 will skip stop and continue with next data 107 reg [
7:
0]
i2c_dly;
// bit duration-1 (>=2?), 1 unit - 4 mclk periods 110 reg [
3:
0]
bytes_left_send;
// Number of bytes left in register write sequence (not counting sa?) 111 reg [
6:
0]
run_reg_wr;
// run register write [6] - start, [5] - send sa, [4] - send high byte (from table),..[0] - send stop 112 reg [
4:
0]
run_extra_wr;
// continue register write (if more than sa + 4bytes) [4] - byte 3, .. [1]- byte0, [0] - stop 113 reg [
7:
0]
run_reg_rd;
// [7] - start, [6] SA (byte 3), [5] (optional) - RA_msb, [4] - RA_lsb, [3] - restart, [2] - SA, [1] - read bytes, [0] - stop 116 reg [
1:
0]
pre_cmd;
// from i2c_start until run_any_d will be active 119 // wire i2c_next_byte; 125 // wire decode_reg_rd = &seq_rd[7:4]; 126 // wire start_wr_seq_w = !run_extra_wr_d && !decode_reg_rd && read_mem_msb; 131 // wire snd_start_w = run_reg_wr[6] || 1'b0; // add start & restart of read 132 // wire snd_stop_w = run_reg_wr[0] || 1'b0; // add stop of read 133 // wire snd9_w = (|run_reg_wr[5:1]) || 1'b0; // add for read and extra write; 138 // the following signals are mutually exclusive, can be encoded to 2 bits. Invaluid during next_cmd_d 141 reg send_sa_rah;
// send slave address/ high address from the table 143 reg [
6:
0]
rd_sa;
// 7-bit slave address for reading 144 wire [
1:
0]
sel_sr_in = {
// select source for the shift register 147 reg [
8:
0]
sr_in;
// input data for the shift register 149 wire bus_open;
// i2c bus is "open" (START-ed but not STOP-ed) - between multi-byte write if it spans >1 32-bit comands 152 reg next_cmd;
// i2c command (start/stop/data) accepted, proceed to the next stage 153 reg next_cmd_d;
// next cycle after next_cmd (first at new state) 160 reg [
1:
0]
initial_address;
// initial data byte to read: usually 3 but for extra write may be different 162 wire unused;
// unused ackn signal SuppressThisWarning VEditor 165 reg rnw;
// last command was read (not write) - do not increment bytes_left_send 167 // wire dout_stb; // rvalid 170 // assign rvalid = dout_stb && run_reg_rd[1]; 202 // wire pre_next_cmd = (snd_start || snd_stop || snd9) && i2c_rdy; 209 // snd_start <= snd_start_w; // add & i2c_ready? Not really needed as any i2c stage will be busy for long enough 210 // snd_stop <= snd_stop_w; 217 // calculate stages for each type of commands 218 // start and write sa and some bytes, stop if number of bytes <= 4 at the end 222 run_reg_wr[
6],
// slave_addr - always after start 229 // send just bytes (up to 4), stop if nothing left 235 (
bytes_left_send ==
1),
// exactly 1 bytes left (zero should never be left) 246 // reg [ 7:0] run_reg_rd; // [7] - start, [6] SA (byte 3), [5] (optional) - RA_msb, [4] - RA_lsb, [3] - restart, [2] - SA, [1] - read bytes, [0] - stop 248 // if (table_re[2] && tdout[8]) read_address_bytes <= tdout[19]; 251 // if (table_re[2] && tdout[8]) read_data_bytes <= tdout[18:16]; 257 // else if (!run_extra_wr_d && decode_reg_rd && read_mem_msb) run_reg_rd <= 8'h80; 260 run_reg_rd[
7],
// slave_addr - always after start (bit0 = 0) 264 run_reg_rd[
3],
// send slave address with 1 in bit[0] 268 // read sequencer memory byte (for the current word) 281 // calculate snd9 and delay it if waiting for memory using mem_valid, set din[8:0] 341 )
ram18_var_w_var_r_i (
350 .
web (
4'hf),
// input[3:0]
8386read_data_bytesreg[2:0]
8367start_extra_seq_wwire
[1 << LOG2WIDTH_WR-1:0] 11597data_in
8354bytes_left_sendreg[3:0]
[1 << LOG2WIDTH_RD-1:0] 11592data_out
[13-LOG2WIDTH_RD:0] 11589raddr
8324SENSI2C_TBL_NBRD_BITS3
8385read_address_bytesreg
ram18_var_w_var_r_i ram18_var_w_var_r
sensor_i2c_scl_sda_i sensor_i2c_scl_sda
[13-LOG2WIDTH_WR:0] 11594waddr
8352num_bytes_sendreg[3:0]
8387initial_addressreg[1:0]
8317SENSI2C_TBL_RAH_BITS8
8322SENSI2C_TBL_NBWR_BITS4
8388initial_address_wwire[3:0]
8327SENSI2C_TBL_DLY_BITS8