44 input ipclk,
// half HiSPi recovered clock (165 MHz for 660 bps of MT9F002) 45 input irst,
// reset sync to ipclk 46 input [
3:
0]
din,
// @posedge ipclk, din[3] came first 47 output reg [
11:
0]
dout,
// 12-bit data output 48 output reg dv,
// data valid - continuous marks line 49 output reg embed,
// valid @sol and up through all dv 50 output reg sof,
// always before first sol - not instead of 51 output reg eof,
// always after last eol (not instead of) 52 output reg sol,
// start of line - 1 cycle before dv 53 output reg eol // end of line - last dv 58 // localparam [3:0] SYNC_EOL = 6; 66 reg [
3:
0]
d_r;
// rehistered input data 68 wire [
2:
0]
num_lead_0_w;
// number of leading 0-s in the last nibble 70 wire [
2:
0]
num_lead_1_w;
// number of leading 1-s in the last nibble 76 reg [
1:
0]
shift_val;
// barrel shifter select (0 is 4!) 80 reg [
3:
0]
sync_decode;
// 1-hot decoding of the last sync word 100 // assign zero_after_ones_w = !((din[0] && !din[1]) || (din[1] && !din[2]) || (din[2] && !din[3]) || (d_r[3] && !din[0])); 108 // first stage - get at least 12 consecutive 1-s, expecting many consecutive 0-s after, so any 109 // 1 after zero should restart counting. 112 // keep number of running 1-s saturated to 12 (to prevent roll over). Temporary there could be 13..15 113 // When running 1-s turn to running zeros, the count will not reset and stay on through counting 114 // of 0-s (will only reset by 1 after 0) 117 // Now count consecutive 0-s after (>=12) 1-s. Not using zero_after_ones in the middle of the run - will 118 // rely on the number of running ones being reset in that case 119 // Saturate number with 24 (5'h18), but only first transition from <24 to >=24 is used for sync 122 // else if (!num_running_ones[2]) num_running_zeros <= {2'b0,num_trail_0_w}; 129 // got_sync should also abort data run - delayed by 10 clocks 132 // else if (got_sync) shift_val <= num_first_zeros; 137 // 2'h1: barrel <= {d_r[2:0], din[3]}; 140 // 2'h3: barrel <= {d_r[0], din[3:1]}; 157 // if (got_sync) got_eol <= 0; 158 // else if (sync_decode[LSB_INDEX] && (barrel == SYNC_EOL)) got_eol <= 1; 199 .
rst (
1'b0),
// input 200 .
dly (
4'h8),
// input[3:0] 206 )
dly_16_pre_start_line_i (
208 .
rst (
1'b0),
// input 209 .
dly (
4'h7),
// input[3:0]
7272num_lead_0_wwire[2:0]
7274num_lead_1_wwire[2:0]
7291num_running_zeros_wwire[4:0]
7271num_trail_0_wwire[2:0]
7269MSB_INDEXHISPI_MSB_FIRST ? 0 : 2
[3:0] 7266SYNC_EOFHISPI_MSB_FIRST ? 4'h7 : 4'he
7273num_trail_1_wwire[2:0]
[3:0] 7267SYNC_EMBEDHISPI_MSB_FIRST ? 4'h1 : 4'h8
[3:0] 7265SYNC_SOLHISPI_MSB_FIRST ? 4'h1 : 4'h8
7276num_running_onesreg[3:0]
7279num_first_zerosreg[1:0]
7268LSB_INDEXHISPI_MSB_FIRST ? 2 : 0
dly_16_pre_start_line_i dly_16
7277num_running_zerosreg[4:0]
7275zero_after_ones_wwire
[3:0] 7264SYNC_SOFHISPI_MSB_FIRST ? 4'h3 : 4'hc