Static Public Member Functions

Always Constructs
ALWAYS_674	( clk )
ALWAYS_675	( clk )
ALWAYS_676	( clk )
ALWAYS_677	( clk )
ALWAYS_678	( clk )
ALWAYS_679	( clk )
ALWAYS_680	( clk )
ALWAYS_681	( clk )
ALWAYS_682	( clk )
ALWAYS_683	( clk )
ALWAYS_684	( clk )
ALWAYS_685	( clk )
ALWAYS_686	( clk )

Public Attributes

Inputs
clk	wire
rst	wire
rxcominitdet_in	wire
rxcomwakedet_in	wire
rxelecidle_in	wire
recal_tx_done	wire
rxreset_ack	wire
clk_phase_align_ack	wire
txdata_in	wire [DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**
txcharisk_in	wire [DATA_BYTE_WIDTH - 1 : 0 ]
rxdata_in	wire [DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**
rxcharisk_in	wire [DATA_BYTE_WIDTH - 1 : 0 ]
oob_start	wire
cominit_allow	wire

Outputs
debug	reg [ 11 : 0 ]
txcominit	wire
txcomwake	wire
txelecidle	wire
txpcsreset_req	wire
rxreset_req	wire
clk_phase_align_req	wire
txdata_out	wire [DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**
txcharisk_out	wire [DATA_BYTE_WIDTH - 1 : 0 ]
rxdata_out	wire [DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**
rxcharisk_out	wire [DATA_BYTE_WIDTH - 1 : 0 ]
oob_done	wire
oob_busy	wire
link_up	wire
link_down	wire
cominit_req	wire
oob_incompatible	wire
oob_error	wire
oob_silence	wire
debug_detected_alignp

Parameters
DATA_BYTE_WIDTH	4
CLK_SPEED_GRADE	1
CLK_TO_TIMER_CONTRIB	[ 19 : 0 ] CLK_SPEED_GRADE == 1 ? 20 'h4 : CLK_SPEED_GRADE == 2 ? 20 'h2 : CLK_SPEED_GRADE == 4 ? 20 'h1 : 20 'h1
RXDLYSRESET_CYCLES	5
TIMER_LIMIT	[ 19 : 0 ] 19 'd262140
NUM_CON_ALIGNS	2
COMINIT_DONE_TIME	896
COMWAKE_DONE_TIME	448

GENERATE
GENERATE [335]
GENERATE [420]

Signals
reg[RXDLYSRESET_CYCLES - 1 : 0 ]	rxdlysreset_r
reg[ 19 : 0 ]	timer
wire	timer_clr
wire	timer_fin
reg	rxcominitdet
reg	rxcomwakedet
reg	rxelecidle
reg[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	rxdata
reg[DATA_BYTE_WIDTH - 1 : 0 ]	rxcharisk
wire	detected_alignp
reg[ 1 : 0 ]	detected_alignp_cntr
reg	detected_alignp_r
wire	detected_syncp
reg	cominit_req_l
reg	rxcominitdet_l
reg	rxcomwakedet_l
wire	rxcominit_done
wire	rxcomwake_done
reg[ 9 : 0 ]	rxcom_timer
reg[ 7 : 0 ]	eidle_timer
wire	eidle_timer_done
wire	state_idle
reg	state_wait_cominit
reg	state_wait_comwake
reg	state_recal_tx
reg	state_wait_eidle
reg	state_wait_rxrst
reg	state_wait_align
reg	state_wait_clk_align
reg	state_wait_align2
reg	state_wait_synp
reg	state_wait_linkup
reg	state_error
wire	set_wait_cominit
wire	set_wait_comwake
wire	set_recal_tx
wire	set_wait_eidle
wire	set_wait_rxrst
wire	set_wait_align
wire	set_wait_clk_align
wire	set_wait_align2
wire	set_wait_synp
wire	set_wait_linkup
wire	set_error
wire	clr_wait_cominit
wire	clr_wait_comwake
wire	clr_recal_tx
wire	clr_wait_eidle
wire	clr_wait_rxrst
wire	clr_wait_align
wire	clr_wait_clk_align
wire	clr_wait_align2
wire	clr_wait_synp
wire	clr_wait_linkup
wire	clr_error
reg	txelecidle_r
reg	rxelecidle_r
reg	rxelecidle_rr
reg	cominit_req_r
wire	cominit_req_set
wire[ 63 : 0 ]	alignp
wire[ 63 : 0 ]	syncp
reg[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	txdata
reg[DATA_BYTE_WIDTH - 1 : 0 ]	txcharisk
wire[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	txdata_d102
wire[DATA_BYTE_WIDTH - 1 : 0 ]	txcharisk_d102
wire[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	txdata_align
wire[DATA_BYTE_WIDTH - 1 : 0 ]	txcharisk_align