x393
1.0
FPGAcodeforElphelNC393camera
oddr_ss.v
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1
39
`timescale 1ns/1ps
40
41
module
oddr_ss
#(
42
parameter
IOSTANDARD
=
"DEFAULT"
,
43
parameter
SLEW
=
"SLOW"
,
44
parameter
DDR_CLK_EDGE
=
"OPPOSITE_EDGE"
,
45
parameter
INIT
=
1'b0
,
46
parameter
SRTYPE
=
"SYNC"
47
)(
48
input
clk
,
49
input
ce
,
50
input
rst
,
51
input
set
,
52
input
[
1
:
0
]
din
,
53
input
tin
,
// tristate control
54
output
dq
55
);
56
wire
idq
;
57
ODDR
#(
58
.
DDR_CLK_EDGE
(
DDR_CLK_EDGE
),
59
.
INIT
(
INIT
),
60
.
SRTYPE
(
SRTYPE
)
61
)
ODDR_i
(
62
.
Q
(
idq
),
// output
63
.
C
(
clk
),
// input
64
.
CE
(
ce
),
// input
65
.
D1
(
din
[
0
]),
// input
66
.
D2
(
din
[
1
]),
// input
67
.
R
(
rst
),
// input
68
.
S
(
set
)
// input
69
);
70
OBUFT
#(
71
.
IOSTANDARD
(
IOSTANDARD
),
72
.
SLEW
(
SLEW
)
73
)
iobufs_i
(
74
.
O
(
dq
),
75
.
I
(
idq
),
76
.
T
(
tin
));
77
endmodule
78
oddr_ss.11504rst
11504rst
Definition:
oddr_ss.v:50
oddr_ss.11507tin
11507tin
Definition:
oddr_ss.v:53
oddr_ss.11500INIT
11500INIT1'b0
Definition:
oddr_ss.v:45
oddr_ss.11506din
[1:0] 11506din
Definition:
oddr_ss.v:52
oddr_ss.ODDR
ODDR_i ODDR
Definition:
oddr_ss.v:57
oddr_ss.11501SRTYPE
11501SRTYPE"SYNC"
Definition:
oddr_ss.v:46
oddr_ss
Definition:
oddr_ss.v:41
oddr_ss.11498SLEW
11498SLEW"SLOW"
Definition:
oddr_ss.v:43
oddr_ss.11509idq
11509idqwire
Definition:
oddr_ss.v:56
oddr_ss.11503ce
11503ce
Definition:
oddr_ss.v:49
oddr_ss.11508dq
11508dq
Definition:
oddr_ss.v:54
oddr_ss.11497IOSTANDARD
11497IOSTANDARD"DEFAULT"
Definition:
oddr_ss.v:42
oddr_ss.11505set
11505set
Definition:
oddr_ss.v:51
oddr_ss.11502clk
11502clk
Definition:
oddr_ss.v:48
oddr_ss.11499DDR_CLK_EDGE
11499DDR_CLK_EDGE"OPPOSITE_EDGE"
Definition:
oddr_ss.v:44
oddr_ss.OBUFT
iobufs_i OBUFT
Definition:
oddr_ss.v:70
wrap
oddr_ss.v
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