43 input mclk,
// system clock, negedge TODO:COnvert to posedge! 44 input xclk,
// half frequency (80 MHz nominal) 46 input we_ra,
// write enable for registers to log (@negedge clk) 47 input we_div,
// write enable for clock dividing(@negedge clk) 48 input we_period,
// write enable for IMU cycle period(@negedge clk) 0 - disable, 1 - single, >1 - half bit periods 49 input [
4:
0]
wa,
// write address for register (5 bits, @negedge clk) 51 output mosi,
// to IMU, bit 2 in J9 52 input miso,
// from IMU, bit 3 on J9 54 output sda,
// sda, shared with i2c, bit 1 55 output sda_en,
// enable sda output (when sda==0 and 1 cycle after sda 0->1) 56 output scl,
// scl, shared with i2c, bit 0 57 output scl_en,
// enable scl output (when scl==0 and 1 cycle after sda 0->1) 58 output ts,
// timestamop request 59 output rdy,
// data ready 60 input rd_stb,
// data read strobe (increment address) 61 output [
15:
0]
rdata);
// data out (16 bits) 63 input mclk; // system clock, negedge 64 input xclk; // half frequency (80 MHz nominal) 65 input we_ra; // write enable for registers to log (@negedge mclk) 66 input we_div;// write enable for clock dividing(@negedge mclk) 67 input we_period;// write enable for IMU cycle period(@negedge clk) 68 input [4:0] wa; // write address for register (5 bits, @negedge mclk) 69 input [15:0] di; // 16-bit data in 70 output mosi; // to IMU, bit 2 in J9 71 input miso; // from IMU, bit 3 on J9 72 input [3:0] config_debug; 73 output sda; // sda, shared with i2c, bit 1 74 output sda_en; // enable sda output (when sda==0 and 1 cycle after sda 0->1) 75 output scl; // scl, shared with i2c, bit 0 76 output scl_en; // enable scl output (when scl==0 and 1 cycle after sda 0->1) 77 output ts; // timestamp request 79 output rdy; // encoded nmea data ready 80 input rd_stb; // encoded nmea data read strobe (increment address) 81 output [15:0] rdata; // encoded data (16 bits) 82 // output sngl_wire; // combined clock/data 91 reg [
4:
0]
imu_in_word=
5'b0;
// number of IMU output word in a sample (0..31), 0..3 - timestamp 98 reg [
1:
0]
seq_state;
// 0 - idle, 1 - prepare spi(4?), 2 - spi-comm(32*29), 3 - finish (2) 110 reg last_bit;
// last clk _/~ in spi word (but first one) 116 reg ts_r;
// delay imu_start by one cycle, so it will be after rdy is reset 118 reg [
31:
0]
period;
// 0 - disable, 1 - single, >1 - period in 50 ns steps 142 reg stall;
// stall between words to satisfy SPI stall time 143 reg [
7:
0]
stall_cntr;
// stall counter (in half mclk periods) 180 // di_d[15:0] <= di[15:0]; 195 // debounce imu_data_ready 278 // set_mosi_spi <= clk_en[2] && (seq_state[1:0]==2'h2) && (seq_counter[4:0]==5'h1f) && (seq_counter[9:5]!=6'h0) && !stall; // last word use zero 281 // no stall before the first word 293 // stall switches at clk_en[2] 294 // stall switches at clk_en[1] 364 myRAM_WxD_D #( .DATA_WIDTH(6),.DATA_DEPTH(5)) 365 i_registers2log (.D(di_d[6:1]), 369 .AR(reg_seq_number[4:0]), 371 .QR(imu_reg_number[6:1])); 379 myRAM_WxD_D #( .DATA_WIDTH(16),.DATA_DEPTH(5)) 380 i_odbuf0 (.D(imu_in_buf[15:0]), 383 .AW(imu_in_word[4:0]), 3673period_counterreg[31:0]
3677first_prepare_dreg[1:0]
3667imu_when_readyreg[1:0]
3640imu_reg_numberwire[6:1]
3688imu_ready_denoise_countreg[6:0]
3670imu_start_grantreg[1:0]
3672imu_start_first_wasreg
3629bit_duration_mclkreg[7:0]
3666imu_when_ready_mclkreg
3631bit_duration_cntrreg[7:0]
3639reg_seq_numberreg[4:0]
3696config_single_wirewire
3691seq_state_zeroreg[1:0]
[0:31] 3698odbuf0_ramreg[15:0]
3648pre_seq_counter_zeroreg
3680stall_dur_mclkreg[7:0]
3690imu_data_readyreg[5:0]
3689imu_data_ready_dreg[2:0]
3678config_long_sda_enwire
3693sngl_wire_stbreg[2:0]
[0:31] 3697registers2log_ramreg[5:0]