46 input rst,
// async reset, active high (global) 47 input rrst,
// @ posedge rclk - sync reset 48 input wrst,
// @ posedge wclk - sync reset 49 input rclk,
// read clock - positive edge 50 input wclk,
// write clock - positive edge 51 input we,
// write enable 52 input re,
// read enable 55 output nempty,
// FIFO has some data (sync to rclk) 56 output half_empty // FIFO half full (wclk) -(not more than 5/8 full) 62 reg [
DATA_DEPTH-
1:
0]
waddr_gray;
//SuppressThisWarning ISExst VivadoSynthesis : MSB(waddr_gray) == MSB(waddr) 70 reg [
2:
0]
raddr_gray_top3;
//SuppressThisWarning ISExst VivadoSynthesis : MSB(raddr_gray_top3) == MSB(raddr) 78 // half-empty does not need to be precise, it uses 3 MSBs of the write address 79 // converting to Gray code (easy) and then back (can not be done parallel easily). 80 // Comparing to 1/8'th of the depth with one-bit Gray code error results in uncertainty 81 // of +/-1/8, so half_empty means "no more than 5/8 full" 83 // False positive in nempty can only happen if 84 // a) it is transitioning from empty to non-empty due to we pulse 85 // b) it is transitioning to overrun - too bad already 86 // false negative - OK, just wait for the next rclk 87 // assign nempty=waddr_gray_rclk != raddr_gray; 88 // assign nempty=waddr_gray_rclk[3:0] != raddr_gray[3:0]; 91 always @ (
posedge wclk or posedge rst)
begin 103 // making rrst set FIFO to empty regardless of current waddr (write should be stopped) 10415raddr_graywire[DATA_DEPTH-1:0]
10419raddr_gray_top3_wclkreg[2:0]
10420raddr_top3_wclkwire[2:0]
[DATA_WIDTH-1:0] 10404data_out
integer 10394DATA_WIDTH16
10409raddrreg[DATA_DEPTH-1:0]
10412waddr_gray_rclkreg[DATA_DEPTH-1:0]
10416raddr_plus1wire[DATA_DEPTH-1:0]
10417raddr_plus1_gray_top3wire[2:0]
[0:DATA_2DEPTH] 10408ramreg[DATA_WIDTH-1:0]
10411waddr_grayreg[DATA_DEPTH-1:0]
[DATA_WIDTH-1:0] 10403data_in
10414waddr_plus1_graywire[DATA_DEPTH-1:0]
integer 10407DATA_2DEPTH(1<<DATA_DEPTH)-1
10410waddrreg[DATA_DEPTH-1:0]
10418raddr_gray_top3reg[2:0]
10413waddr_plus1wire[DATA_DEPTH-1:0]