Static Public Member Functions

Always Constructs
ALWAYS_356	( pclk )
ALWAYS_357	( pclk )
ALWAYS_358	( mclk )
ALWAYS_359	( pclk )
ALWAYS_360	( pclk )
ALWAYS_361	( pclk2x )
ALWAYS_362	( pclk2x )
ALWAYS_363	( mclk )
ALWAYS_364	( pclk )

Public Attributes

Inputs
mrst
prst
pclk
pclk2x
sof
eof
hact
hist_di	[ 7 : 0 ]
mclk
hist_en
hist_rst
hist_grant
cmd_ad	[ 7 : 0 ]
cmd_stb
monochrome
debug_sl
debug_di

Outputs
hist_rq
hist_do	[ 31 : 0 ]
hist_dv
debug_do

Parameters
HISTOGRAM_RAM_MODE	"BUF32"
HISTOGRAM_ADDR	'h33c
HISTOGRAM_ADDR_MASK	'h7fe
HISTOGRAM_LEFT_TOP	'h0
HISTOGRAM_WIDTH_HEIGHT	'h1
7299
7300
PXD_2X_LATENCY	2

GENERATE
GENERATE [455]

Signals
reg	hist_bank_pclk
reg[ 9 : 0 ]	hist_addr
reg[ 9 : 0 ]	hist_addr_d
reg[ 9 : 0 ]	hist_addr_d2
reg[ 9 : 0 ]	hist_rwaddr
reg[ 31 : 0 ]	to_inc
reg[ 31 : 0 ]	inc_r
reg[ 31 : 0 ]	inc_sat
wire[ 31 : 0 ]	hist_new
reg	hist_rwen
reg[ 1 : 0 ]	hist_regen
reg	hist_we
reg	hist_bank_mclk
wire	set_left_top_w
wire	set_width_height_w
wire[ 1 : 0 ]	pio_addr
wire[ 31 : 0 ]	pio_data
wire	pio_stb
reg[ 31 : 0 ]	lt_mclk
reg[ 31 : 0 ]	wh_mclk
reg[ 15 : 0 ]	width_m1
reg[ 15 : 0 ]	height_m1
reg[ 15 : 0 ]	left
reg[ 15 : 0 ]	top
reg	hist_en_pclk
reg	hist_rst_pclk
reg	en
reg	en_new
reg	en_mclk
wire	set_left_top_pclk
wire	set_width_height_pclk
reg	pclk_sync
reg[ 1 : 0 ]	bayer_pclk
reg[ 1 : 0 ]	hact_d
reg	top_margin
reg	hist_done
wire	hist_done_mclk
reg	vert_woi
reg	left_margin
reg[ 2 : 0 ]	woi
reg	hor_woi
reg[ 15 : 0 ]	vcntr
reg[ 15 : 0 ]	hcntr
wire	vcntr_zero_w
wire	hcntr_zero_w
reg	same_addr1
reg	same_addr2
reg	hist_out
reg	hist_out_d
reg[ 2 : 0 ]	hist_re
reg[ 9 : 0 ]	hist_raddr
reg	hist_rq_r
wire	hist_xfer_done_mclk
wire	hist_xfer_done
reg	hist_xfer_busy
reg	wait_readout
reg[ 15 : 0 ]	debug_line_cntr
reg[ 15 : 0 ]	debug_lines
wire	line_start_w
reg	pre_first_line
reg	frame_active
reg	hist_en_pclk2x
wire	hlstart
reg[ 7 : 0 ]	pxd_ram [ 0 : 15 ]
reg[ 1 : 0 ]	bayer_ram [ 0 : 15 ]
reg[ 0 : 0 ]	woi_ram [ 0 : 15 ]
reg[ 3 : 0 ]	pxd_wa
reg[ 3 : 0 ]	pxd_wa_woi
reg[ 3 : 0 ]	pxd_ra
reg[ 3 : 0 ]	pxd_ra_start
wire[ 1 : 0 ]	bayer_2x
wire[ 7 : 0 ]	pxd_2x
wire	hor_woi_2x
reg	monochrome_pclk
reg	monochrome_2x
reg	en_rq_start

Module Instances
debug_slave::debug_slave_i	Module debug_slave
cmd_deser::cmd_deser_sens_histogram_i	Module cmd_deser
pulse_cross_clock::pulse_cross_clock_hlstart_start_i	Module pulse_cross_clock
pulse_cross_clock::pulse_cross_clock_lt_i	Module pulse_cross_clock
pulse_cross_clock::pulse_cross_clock_wh_i	Module pulse_cross_clock
pulse_cross_clock::pulse_cross_clock_hist_done_i	Module pulse_cross_clock
pulse_cross_clock::pulse_cross_clock_hist_xfer_done_i	Module pulse_cross_clock
sens_hist_ram_double::sens_hist_ram_i	Module sens_hist_ram_double [generate]
sens_hist_ram_single::sens_hist_ram_i	Module sens_hist_ram_single [generate]
sens_hist_ram_nobuff::sens_hist_ram_i	Module sens_hist_ram_nobuff [generate]