x393  1.0
FPGAcodeforElphelNC393camera
sens_histogram Member List

This is the complete list of members for sens_histogram, including all inherited members.

SHIFT_WIDTHdebug_slaveParameter
READ_WIDTHdebug_slaveParameter
WRITE_WIDTHdebug_slaveParameter
DEBUG_CMD_LATENCYdebug_slaveParameter
mclkdebug_slaveInput
mrstdebug_slaveInput
debug_didebug_slaveInput
debug_sldebug_slaveInput
debug_dodebug_slaveOutput
rd_datadebug_slaveInput
wr_datadebug_slaveOutput
stbdebug_slaveOutput
data_srdebug_slaveSignal
cmddebug_slaveSignal
cmd_regdebug_slaveSignal
cmd_reg_dlydebug_slaveSignal
ext_rdatadebug_slaveSignal
EXTRA_DLYpulse_cross_clockParameter
rstpulse_cross_clockInput
src_clkpulse_cross_clockInput
dst_clkpulse_cross_clockInput
in_pulsepulse_cross_clockInput
out_pulsepulse_cross_clockOutput
busypulse_cross_clockOutput
EXTRA_DLY_SAFEpulse_cross_clockParameter
in_regpulse_cross_clockSignal
out_regpulse_cross_clockSignal
busy_rpulse_cross_clockSignal
REGISTERS_Aramt_var_w_var_rParameter
REGISTERS_Bramt_var_w_var_rParameter
LOG2WIDTH_Aramt_var_w_var_rParameter
LOG2WIDTH_Bramt_var_w_var_rParameter
WRITE_MODE_Aramt_var_w_var_rParameter
12038ramt_var_w_var_rParameter
clk_aramt_var_w_var_rInput
addr_aramt_var_w_var_rInput
en_aramt_var_w_var_rInput
regen_aramt_var_w_var_rInput
we_aramt_var_w_var_rInput
data_out_aramt_var_w_var_rOutput
data_in_aramt_var_w_var_rInput
clk_bramt_var_w_var_rInput
addr_bramt_var_w_var_rInput
en_bramt_var_w_var_rInput
regen_bramt_var_w_var_rInput
we_bramt_var_w_var_rInput
data_out_bramt_var_w_var_rOutput
data_in_bramt_var_w_var_rInput
PWIDTH_Aramt_var_w_var_rParameter
PWIDTH_Bramt_var_w_var_rParameter
WIDTH_Aramt_var_w_var_rParameter
WIDTH_Bramt_var_w_var_rParameter
data_out32_aramt_var_w_var_rSignal
data_out32_bramt_var_w_var_rSignal
data_in_ext_aramt_var_w_var_rSignal
data_in32_aramt_var_w_var_rSignal
data_in_ext_bramt_var_w_var_rSignal
data_in32_bramt_var_w_var_rSignal
HISTOGRAM_RAM_MODEsens_histogram
HISTOGRAM_ADDRsens_histogram
HISTOGRAM_ADDR_MASKsens_histogram
HISTOGRAM_LEFT_TOPsens_histogram
HISTOGRAM_WIDTH_HEIGHTsens_histogram
7299sens_histogram
7300sens_histogram
mrstsens_histogram
prstsens_histogram
pclksens_histogram
pclk2xsens_histogram
sofsens_histogram
eofsens_histogram
hactsens_histogram
hist_disens_histogram
mclksens_histogram
hist_ensens_histogram
hist_rstsens_histogram
hist_rqsens_histogram
hist_grantsens_histogram
hist_dosens_histogram
hist_dvsens_histogram
cmd_adsens_histogram
cmd_stbsens_histogram
monochromesens_histogram
debug_dosens_histogram
debug_slsens_histogram
debug_disens_histogram
PXD_2X_LATENCYsens_histogram
hist_bank_pclksens_histogram
hist_addrsens_histogram
hist_addr_dsens_histogram
hist_addr_d2sens_histogram
hist_rwaddrsens_histogram
to_incsens_histogram
inc_rsens_histogram
inc_satsens_histogram
hist_newsens_histogram
hist_rwensens_histogram
hist_regensens_histogram
hist_wesens_histogram
hist_bank_mclksens_histogram
set_left_top_wsens_histogram
set_width_height_wsens_histogram
pio_addrsens_histogram
pio_datasens_histogram
pio_stbsens_histogram
lt_mclksens_histogram
wh_mclksens_histogram
width_m1sens_histogram
height_m1sens_histogram
leftsens_histogram
topsens_histogram
hist_en_pclksens_histogram
hist_rst_pclksens_histogram
ensens_histogram
en_newsens_histogram
en_mclksens_histogram
set_left_top_pclksens_histogram
set_width_height_pclksens_histogram
pclk_syncsens_histogram
bayer_pclksens_histogram
hact_dsens_histogram
top_marginsens_histogram
hist_donesens_histogram
hist_done_mclksens_histogram
vert_woisens_histogram
left_marginsens_histogram
woisens_histogram
hor_woisens_histogram
vcntrsens_histogram
hcntrsens_histogram
vcntr_zero_wsens_histogram
hcntr_zero_wsens_histogram
same_addr1sens_histogram
same_addr2sens_histogram
hist_outsens_histogram
hist_out_dsens_histogram
hist_resens_histogram
hist_raddrsens_histogram
hist_rq_rsens_histogram
hist_xfer_done_mclksens_histogram
hist_xfer_donesens_histogram
hist_xfer_busysens_histogram
wait_readoutsens_histogram
debug_line_cntrsens_histogram
debug_linessens_histogram
line_start_wsens_histogram
pre_first_linesens_histogram
frame_activesens_histogram
hist_en_pclk2xsens_histogram
hlstartsens_histogram
pxd_ramsens_histogram
bayer_ramsens_histogram
woi_ramsens_histogram
pxd_wasens_histogram
pxd_wa_woisens_histogram
pxd_rasens_histogram
pxd_ra_startsens_histogram
bayer_2xsens_histogram
pxd_2xsens_histogram
hor_woi_2xsens_histogram
monochrome_pclksens_histogram
monochrome_2xsens_histogram
en_rq_startsens_histogram
pclk2xsens_hist_ram_singleInput
addr_asens_hist_ram_singleInput
data_in_asens_hist_ram_singleInput
data_out_asens_hist_ram_singleOutput
en_asens_hist_ram_singleInput
regen_asens_hist_ram_singleInput
we_asens_hist_ram_singleInput
mclksens_hist_ram_singleInput
addr_bsens_hist_ram_singleInput
data_out_bsens_hist_ram_singleOutput
re_bsens_hist_ram_singleInput
regen_bsens_hist_ram_singleInput
data_out_a18sens_hist_ram_singleSignal
data_out_b18sens_hist_ram_singleSignal
pclk2xsens_hist_ram_doubleInput
addr_asens_hist_ram_doubleInput
data_in_asens_hist_ram_doubleInput
data_out_asens_hist_ram_doubleOutput
en_asens_hist_ram_doubleInput
regen_asens_hist_ram_doubleInput
we_asens_hist_ram_doubleInput
mclksens_hist_ram_doubleInput
addr_bsens_hist_ram_doubleInput
data_out_bsens_hist_ram_doubleOutput
re_bsens_hist_ram_doubleInput
regen_bsens_hist_ram_doubleInput
pclk2xsens_hist_ram_nobuffInput
addr_asens_hist_ram_nobuffInput
data_in_asens_hist_ram_nobuffInput
data_out_asens_hist_ram_nobuffOutput
en_asens_hist_ram_nobuffInput
regen_asens_hist_ram_nobuffInput
we_asens_hist_ram_nobuffInput
mclksens_hist_ram_nobuffInput
addr_bsens_hist_ram_nobuffInput
data_out_bsens_hist_ram_nobuffOutput
re_bsens_hist_ram_nobuffInput
regen_bsens_hist_ram_nobuffInput
ADDRcmd_deserParameter
ADDR_MASKcmd_deserParameter
NUM_CYCLEScmd_deserParameter
ADDR_WIDTHcmd_deserParameter
DATA_WIDTHcmd_deserParameter
ADDR1cmd_deserParameter
ADDR_MASK1cmd_deserParameter
ADDR2cmd_deserParameter
ADDR_MASK2cmd_deserParameter
WE_EARLYcmd_deserParameter
rstcmd_deserInput
clkcmd_deserInput
srstcmd_deserInput
adcmd_deserInput
stbcmd_deserInput
addrcmd_deserOutput
datacmd_deserOutput
wecmd_deserOutput
WE_WIDTHcmd_deserParameter
ALWAYS_356 pclksens_histogramAlways Construct
ALWAYS_357 pclksens_histogramAlways Construct
ALWAYS_358 mclksens_histogramAlways Construct
ALWAYS_359 pclksens_histogramAlways Construct
ALWAYS_360 pclksens_histogramAlways Construct
ALWAYS_361 pclk2xsens_histogramAlways Construct
ALWAYS_362 pclk2xsens_histogramAlways Construct
ALWAYS_363 mclksens_histogramAlways Construct
ALWAYS_364 pclksens_histogramAlways Construct
ALWAYS_497 mclkdebug_slaveAlways Construct
ALWAYS_532 src_clk or rstpulse_cross_clockAlways Construct
ALWAYS_533 dst_clkpulse_cross_clockAlways Construct
cmd_desersens_histogram
cmd_deser_dualcmd_deserModule Instance
cmd_deser_multicmd_deserModule Instance
cmd_deser_singlecmd_deserModule Instance
debug_slavesens_histogram
GENERATE [455]sens_histogram
GENERATE [63]cmd_deserGENERATE
pulse_cross_clocksens_histogram
pulse_cross_clocksens_histogram
pulse_cross_clocksens_histogram
pulse_cross_clocksens_histogram
pulse_cross_clocksens_histogram
sens_hist_ram_single.ram36_declare_init.vhramtp_var_w_var_rInclude
sens_hist_ram_nobuff.ram36_declare_init.vhramt_var_w_var_rInclude
sens_hist_ram_single.ram36_pass_init.vhramtp_var_w_var_rInclude
sens_hist_ram_nobuff.ram36_pass_init.vhramt_var_w_var_rInclude
sens_hist_ram_single.RAMB36E1ramtp_var_w_var_rModule Instance
sens_hist_ram_nobuff.RAMB36E1ramt_var_w_var_rModule Instance
sens_hist_ram_double.ramt_var_w_var_rsens_hist_ram_doubleModule Instance
sens_hist_ram_double.ramt_var_w_var_rsens_hist_ram_doubleModule Instance
sens_hist_ram_nobuff.ramt_var_w_var_rsens_hist_ram_nobuffModule Instance
ramtp_var_w_var_rsens_hist_ram_singleModule Instance
sens_hist_ram_doublesens_histogram
sens_hist_ram_nobuffsens_histogram
sens_hist_ram_singlesens_histogram