x393
1.0
FPGAcodeforElphelNC393camera
sens_hispi_clock Member List
This is the complete list of members for
sens_hispi_clock
, including all inherited members.
CAPACITANCE
ibufds_ibufgds
Parameter
DIFF_TERM
ibufds_ibufgds
Parameter
DQS_BIAS
ibufds_ibufgds
Parameter
IBUF_DELAY_VALUE
ibufds_ibufgds
Parameter
IBUF_LOW_PWR
ibufds_ibufgds
Parameter
IFD_DELAY_VALUE
ibufds_ibufgds
Parameter
IOSTANDARD
ibufds_ibufgds
Parameter
O
ibufds_ibufgds
Output
I
ibufds_ibufgds
Input
IB
ibufds_ibufgds
Input
CAPACITANCE
ibufds_ibufgds_50
Parameter
DIFF_TERM
ibufds_ibufgds_50
Parameter
DQS_BIAS
ibufds_ibufgds_50
Parameter
IBUF_DELAY_VALUE
ibufds_ibufgds_50
Parameter
IBUF_LOW_PWR
ibufds_ibufgds_50
Parameter
IFD_DELAY_VALUE
ibufds_ibufgds_50
Parameter
IOSTANDARD
ibufds_ibufgds_50
Parameter
O
ibufds_ibufgds_50
Output
I
ibufds_ibufgds_50
Input
IB
ibufds_ibufgds_50
Input
IODELAY_GRP
idelay_nofine
Parameter
DELAY_VALUE
idelay_nofine
Parameter
REFCLK_FREQUENCY
idelay_nofine
Parameter
HIGH_PERFORMANCE_MODE
idelay_nofine
Parameter
clk
idelay_nofine
Input
rst
idelay_nofine
Input
set
idelay_nofine
Input
ld
idelay_nofine
Input
delay
idelay_nofine
Input
data_in
idelay_nofine
Input
data_out
idelay_nofine
Output
PHASE_WIDTH
mmcm_phase_cntr
Parameter
CLKIN_PERIOD
mmcm_phase_cntr
Parameter
BANDWIDTH
mmcm_phase_cntr
Parameter
CLKFBOUT_MULT_F
mmcm_phase_cntr
Parameter
CLKFBOUT_PHASE
mmcm_phase_cntr
Parameter
CLKOUT0_PHASE
mmcm_phase_cntr
Parameter
CLKOUT1_PHASE
mmcm_phase_cntr
Parameter
CLKOUT2_PHASE
mmcm_phase_cntr
Parameter
CLKOUT3_PHASE
mmcm_phase_cntr
Parameter
CLKOUT4_PHASE
mmcm_phase_cntr
Parameter
CLKOUT5_PHASE
mmcm_phase_cntr
Parameter
CLKOUT6_PHASE
mmcm_phase_cntr
Parameter
CLKOUT0_DUTY_CYCLE
mmcm_phase_cntr
Parameter
CLKOUT1_DUTY_CYCLE
mmcm_phase_cntr
Parameter
CLKOUT2_DUTY_CYCLE
mmcm_phase_cntr
Parameter
CLKOUT3_DUTY_CYCLE
mmcm_phase_cntr
Parameter
CLKOUT4_DUTY_CYCLE
mmcm_phase_cntr
Parameter
CLKOUT5_DUTY_CYCLE
mmcm_phase_cntr
Parameter
CLKOUT6_DUTY_CYCLE
mmcm_phase_cntr
Parameter
CLKOUT4_CASCADE
mmcm_phase_cntr
Parameter
CLKFBOUT_USE_FINE_PS
mmcm_phase_cntr
Parameter
CLKOUT0_USE_FINE_PS
mmcm_phase_cntr
Parameter
CLKOUT1_USE_FINE_PS
mmcm_phase_cntr
Parameter
CLKOUT2_USE_FINE_PS
mmcm_phase_cntr
Parameter
CLKOUT3_USE_FINE_PS
mmcm_phase_cntr
Parameter
CLKOUT4_USE_FINE_PS
mmcm_phase_cntr
Parameter
CLKOUT5_USE_FINE_PS
mmcm_phase_cntr
Parameter
CLKOUT6_USE_FINE_PS
mmcm_phase_cntr
Parameter
CLKOUT0_DIVIDE_F
mmcm_phase_cntr
Parameter
CLKOUT1_DIVIDE
mmcm_phase_cntr
Parameter
CLKOUT2_DIVIDE
mmcm_phase_cntr
Parameter
CLKOUT3_DIVIDE
mmcm_phase_cntr
Parameter
CLKOUT4_DIVIDE
mmcm_phase_cntr
Parameter
CLKOUT5_DIVIDE
mmcm_phase_cntr
Parameter
CLKOUT6_DIVIDE
mmcm_phase_cntr
Parameter
COMPENSATION
mmcm_phase_cntr
Parameter
DIVCLK_DIVIDE
mmcm_phase_cntr
Parameter
REF_JITTER1
mmcm_phase_cntr
Parameter
REF_JITTER2
mmcm_phase_cntr
Parameter
SS_EN
mmcm_phase_cntr
Parameter
SS_MODE
mmcm_phase_cntr
Parameter
SS_MOD_PERIOD
mmcm_phase_cntr
Parameter
STARTUP_WAIT
mmcm_phase_cntr
Parameter
clkin1
mmcm_phase_cntr
Input
clkin2
mmcm_phase_cntr
Input
sel_clk2
mmcm_phase_cntr
Input
clkfbin
mmcm_phase_cntr
Input
rst
mmcm_phase_cntr
Input
pwrdwn
mmcm_phase_cntr
Input
psclk
mmcm_phase_cntr
Input
ps_we
mmcm_phase_cntr
Input
ps_din
mmcm_phase_cntr
Input
ps_ready
mmcm_phase_cntr
Output
ps_dout
mmcm_phase_cntr
Output
clkout0
mmcm_phase_cntr
Output
clkout1
mmcm_phase_cntr
Output
clkout2
mmcm_phase_cntr
Output
clkout3
mmcm_phase_cntr
Output
clkout4
mmcm_phase_cntr
Output
clkout5
mmcm_phase_cntr
Output
clkout6
mmcm_phase_cntr
Output
clkout0b
mmcm_phase_cntr
Output
clkout1b
mmcm_phase_cntr
Output
clkout2b
mmcm_phase_cntr
Output
clkout3b
mmcm_phase_cntr
Output
clkfbout
mmcm_phase_cntr
Output
clkfboutb
mmcm_phase_cntr
Output
locked
mmcm_phase_cntr
Output
clkin_stopped
mmcm_phase_cntr
Output
clkfb_stopped
mmcm_phase_cntr
Output
ps_dout_r
mmcm_phase_cntr
Signal
psen
mmcm_phase_cntr
Signal
psincdec
mmcm_phase_cntr
Signal
psdone
mmcm_phase_cntr
Signal
ps_target
mmcm_phase_cntr
Signal
ps_busy
mmcm_phase_cntr
Signal
ps_start0
mmcm_phase_cntr
Signal
ps_start
mmcm_phase_cntr
Signal
diff
mmcm_phase_cntr
Signal
reset_extended
mmcm_phase_cntr
Signal
CLKIN_PERIOD
pll_base
Parameter
BANDWIDTH
pll_base
Parameter
CLKFBOUT_MULT
pll_base
Parameter
CLKFBOUT_PHASE
pll_base
Parameter
CLKOUT0_PHASE
pll_base
Parameter
CLKOUT1_PHASE
pll_base
Parameter
CLKOUT2_PHASE
pll_base
Parameter
CLKOUT3_PHASE
pll_base
Parameter
CLKOUT4_PHASE
pll_base
Parameter
CLKOUT5_PHASE
pll_base
Parameter
CLKOUT0_DUTY_CYCLE
pll_base
Parameter
CLKOUT1_DUTY_CYCLE
pll_base
Parameter
CLKOUT2_DUTY_CYCLE
pll_base
Parameter
CLKOUT3_DUTY_CYCLE
pll_base
Parameter
CLKOUT4_DUTY_CYCLE
pll_base
Parameter
CLKOUT5_DUTY_CYCLE
pll_base
Parameter
CLKOUT0_DIVIDE
pll_base
Parameter
CLKOUT1_DIVIDE
pll_base
Parameter
CLKOUT2_DIVIDE
pll_base
Parameter
CLKOUT3_DIVIDE
pll_base
Parameter
CLKOUT4_DIVIDE
pll_base
Parameter
CLKOUT5_DIVIDE
pll_base
Parameter
DIVCLK_DIVIDE
pll_base
Parameter
REF_JITTER1
pll_base
Parameter
STARTUP_WAIT
pll_base
Parameter
clkin
pll_base
Input
clkfbin
pll_base
Input
rst
pll_base
Input
pwrdwn
pll_base
Input
clkout0
pll_base
Output
clkout1
pll_base
Output
clkout2
pll_base
Output
clkout3
pll_base
Output
clkout4
pll_base
Output
clkout5
pll_base
Output
clkfbout
pll_base
Output
locked
pll_base
Output
SENS_PHASE_WIDTH
sens_hispi_clock
SENS_BANDWIDTH
sens_hispi_clock
CLKIN_PERIOD_SENSOR
sens_hispi_clock
CLKFBOUT_MULT_SENSOR
sens_hispi_clock
CLKFBOUT_PHASE_SENSOR
sens_hispi_clock
IPCLK_PHASE
sens_hispi_clock
IPCLK2X_PHASE
sens_hispi_clock
BUF_IPCLK
sens_hispi_clock
BUF_IPCLK2X
sens_hispi_clock
SENS_DIVCLK_DIVIDE
sens_hispi_clock
SENS_REF_JITTER1
sens_hispi_clock
SENS_REF_JITTER2
sens_hispi_clock
SENS_SS_EN
sens_hispi_clock
SENS_SS_MODE
sens_hispi_clock
SENS_SS_MOD_PERIOD
sens_hispi_clock
IODELAY_GRP
sens_hispi_clock
IDELAY_VALUE
sens_hispi_clock
REFCLK_FREQUENCY
sens_hispi_clock
HIGH_PERFORMANCE_MODE
sens_hispi_clock
HISPI_DELAY_CLK
sens_hispi_clock
HISPI_MMCM
sens_hispi_clock
HISPI_CAPACITANCE
sens_hispi_clock
HISPI_DIFF_TERM
sens_hispi_clock
HISPI_UNTUNED_SPLIT
sens_hispi_clock
HISPI_DQS_BIAS
sens_hispi_clock
HISPI_IBUF_DELAY_VALUE
sens_hispi_clock
HISPI_IBUF_LOW_PWR
sens_hispi_clock
HISPI_IFD_DELAY_VALUE
sens_hispi_clock
HISPI_IOSTANDARD
sens_hispi_clock
mclk
sens_hispi_clock
mrst
sens_hispi_clock
phase
sens_hispi_clock
set_phase
sens_hispi_clock
load
sens_hispi_clock
rst_mmcm
sens_hispi_clock
clp_p
sens_hispi_clock
clk_n
sens_hispi_clock
ipclk
sens_hispi_clock
ipclk2x
sens_hispi_clock
ps_rdy
sens_hispi_clock
ps_out
sens_hispi_clock
locked_pxd_mmcm
sens_hispi_clock
clkin_pxd_stopped_mmcm
sens_hispi_clock
clkfb_pxd_stopped_mmcm
sens_hispi_clock
ipclk_pre
sens_hispi_clock
ipclk2x_pre
sens_hispi_clock
clk_fb
sens_hispi_clock
prst
sens_hispi_clock
clk_in
sens_hispi_clock
clk_int
sens_hispi_clock
set_phase_w
sens_hispi_clock
phase_w
sens_hispi_clock
ps_rdy_w
sens_hispi_clock
ps_out_w
sens_hispi_clock
ALWAYS_552
psclk
mmcm_phase_cntr
Always Construct
ALWAYS_553
psclk
mmcm_phase_cntr
Always Construct
BUFG
sens_hispi_clock
BUFG
sens_hispi_clock
BUFH
sens_hispi_clock
BUFH
sens_hispi_clock
BUFIO
sens_hispi_clock
BUFIO
sens_hispi_clock
BUFMR
sens_hispi_clock
BUFMR
sens_hispi_clock
BUFR
sens_hispi_clock
BUFR
sens_hispi_clock
GENERATE [106]
sens_hispi_clock
GENERATE [137]
sens_hispi_clock
GENERATE [161]
sens_hispi_clock
GENERATE [251]
sens_hispi_clock
GENERATE [261]
sens_hispi_clock
ibufds_ibufgds_50.IBUFDS
ibufds_ibufgds_50
Module Instance
ibufds_ibufgds.IBUFDS
ibufds_ibufgds
Module Instance
ibufds_ibufgds
sens_hispi_clock
ibufds_ibufgds_50
sens_hispi_clock
idelay_nofine
sens_hispi_clock
IDELAYE2
idelay_nofine
Module Instance
mmcm_phase_cntr
sens_hispi_clock
MMCME2_ADV
mmcm_phase_cntr
Module Instance
pll_base
sens_hispi_clock
PLLE2_ADV
pll_base
Module Instance
Generated by
1.8.12