mult_saxi_wr_inbuf Module Reference

Inheritance diagram for mult_saxi_wr_inbuf:

Collaboration diagram for mult_saxi_wr_inbuf:

Static Public Member Functions

Always Constructs
ALWAYS_38	( iclk )
ALWAYS_39	( mclk )

Public Attributes

Inputs
mclk
en
iclk
data_in	[ 1 << MULT_SAXI_WLOG - 1 : 0 ]
valid
read_burst

Outputs
has_burst	reg
data_out	[ 31 : 0 ]
pre_valid_chn

Parameters
MULT_SAXI_HALF_BRAM_IN	1
MULT_SAXI_BSLOG	4
MULT_SAXI_WLOG	4
INA_WIDTH	(MULT_SAXI_HALF_BRAM_IN ? 14 : 15 ) - MULT_SAXI_WLOG
OUTA_WIDTH	(MULT_SAXI_HALF_BRAM_IN ? 14 : 15 ) - 5
INW_CNTR_WIDTH	MULT_SAXI_BSLOG + 5 -MULT_SAXI_WLOG
OUTW_CNTR_WIDTH	MULT_SAXI_BSLOG
BURST_WIDTH	OUTA_WIDTH - OUTW_CNTR_WIDTH

GENERATE
GENERATE [120]

Signals
reg	en_iclk
reg[INW_CNTR_WIDTH - 1 : 0 ]	inw_cntr
reg[BURST_WIDTH - 1 : 0 ]	in_burst
reg[OUTW_CNTR_WIDTH - 1 : 0 ]	outw_cntr
reg[BURST_WIDTH - 1 : 0 ]	out_burst
reg[BURST_WIDTH : 0 ]	num_out_bursts
wire[INA_WIDTH - 1 : 0 ]	waddr
wire[OUTA_WIDTH - 1 : 0 ]	raddr
wire	put_burst_mclk
wire	wr_last_word
wire	re_last_word
reg[ 1 : 0 ]	buf_re

Module Instances
pulse_cross_clock::put_burst_mclk_i	Module pulse_cross_clock
ram18_var_w_var_r::ram_var_w_var_r_i	Module ram18_var_w_var_r [generate]
ram_var_w_var_r::ram_var_w_var_r_i	Module ram_var_w_var_r [generate]

Detailed Description

Definition at line 41 of file mult_saxi_wr_inbuf.v.

Member Function Documentation

ALWAYS_38 (   iclk   )

Always Construct

Definition at line 83 of file mult_saxi_wr_inbuf.v.

ALWAYS_39 (   mclk   )

Always Construct

Definition at line 93 of file mult_saxi_wr_inbuf.v.

Member Data Documentation

MULT_SAXI_HALF_BRAM_IN 1

Parameter

Definition at line 42 of file mult_saxi_wr_inbuf.v.

MULT_SAXI_BSLOG 4

Parameter

Definition at line 43 of file mult_saxi_wr_inbuf.v.

MULT_SAXI_WLOG 4

Parameter

Definition at line 44 of file mult_saxi_wr_inbuf.v.

mclk

Input

Definition at line 46 of file mult_saxi_wr_inbuf.v.

en

Input

Definition at line 47 of file mult_saxi_wr_inbuf.v.

iclk

Input

Definition at line 50 of file mult_saxi_wr_inbuf.v.

data_in [ 1 << MULT_SAXI_WLOG - 1 : 0 ]

Input

Definition at line 51 of file mult_saxi_wr_inbuf.v.

valid

Input

Definition at line 52 of file mult_saxi_wr_inbuf.v.

has_burst reg

Output

Definition at line 54 of file mult_saxi_wr_inbuf.v.

read_burst

Input

Definition at line 55 of file mult_saxi_wr_inbuf.v.

data_out [ 31 : 0 ]

Output

Definition at line 56 of file mult_saxi_wr_inbuf.v.

pre_valid_chn

Output

Definition at line 57 of file mult_saxi_wr_inbuf.v.

INA_WIDTH (MULT_SAXI_HALF_BRAM_IN ? 14 : 15 ) - MULT_SAXI_WLOG

Parameter

Definition at line 60 of file mult_saxi_wr_inbuf.v.

OUTA_WIDTH (MULT_SAXI_HALF_BRAM_IN ? 14 : 15 ) - 5

Parameter

Definition at line 61 of file mult_saxi_wr_inbuf.v.

INW_CNTR_WIDTH MULT_SAXI_BSLOG + 5 -MULT_SAXI_WLOG

Parameter

Definition at line 62 of file mult_saxi_wr_inbuf.v.

OUTW_CNTR_WIDTH MULT_SAXI_BSLOG

Parameter

Definition at line 63 of file mult_saxi_wr_inbuf.v.

BURST_WIDTH OUTA_WIDTH - OUTW_CNTR_WIDTH

Parameter

Definition at line 64 of file mult_saxi_wr_inbuf.v.

en_iclk

Signal

Definition at line 66 of file mult_saxi_wr_inbuf.v.

inw_cntr

Signal

Definition at line 67 of file mult_saxi_wr_inbuf.v.

in_burst

Signal

Definition at line 68 of file mult_saxi_wr_inbuf.v.

outw_cntr

Signal

Definition at line 69 of file mult_saxi_wr_inbuf.v.

out_burst

Signal

Definition at line 70 of file mult_saxi_wr_inbuf.v.

num_out_bursts

Signal

Definition at line 71 of file mult_saxi_wr_inbuf.v.

waddr

Signal

Definition at line 73 of file mult_saxi_wr_inbuf.v.

raddr

Signal

Definition at line 74 of file mult_saxi_wr_inbuf.v.

put_burst_mclk

Signal

Definition at line 76 of file mult_saxi_wr_inbuf.v.

wr_last_word

Signal

Definition at line 77 of file mult_saxi_wr_inbuf.v.

re_last_word

Signal

Definition at line 79 of file mult_saxi_wr_inbuf.v.

buf_re

Signal

Definition at line 80 of file mult_saxi_wr_inbuf.v.

GENERATE [120]

GENERATE

Definition at line 120 of file mult_saxi_wr_inbuf.v.

pulse_cross_clock put_burst_mclk_i

Module Instance

Definition at line 112 of file mult_saxi_wr_inbuf.v.

ram18_var_w_var_r ram_var_w_var_r_i

Module Instance

Definition at line 122 of file mult_saxi_wr_inbuf.v.

ram_var_w_var_r ram_var_w_var_r_i

Module Instance

Definition at line 140 of file mult_saxi_wr_inbuf.v.

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The documentation for this Module was generated from the following files:

• axi/mult_saxi_wr_inbuf.v