dual_clock_source Module Reference

Inheritance diagram for dual_clock_source:

Collaboration diagram for dual_clock_source:

Public Attributes

Inputs
rst
clk_in
pwrdwn

Outputs
clk1x
clk2x
locked

Parameters
CLKIN_PERIOD	20
DIVCLK_DIVIDE	1
CLKFBOUT_MULT	20
CLKOUT_DIV_CLK1X	10
CLKOUT_DIV_CLK2X	5
PHASE_CLK2X	0 . 000
BUF_CLK1X	"BUFG "
BUF_CLK2X	"BUFG "

GENERATE
GENERATE [61]
GENERATE [70]

Signals
wire	clkfb
wire	clk1x_pre
wire	clk2x_pre

Module Instances
BUFG::clk1x_i	Module BUFG [generate]
BUFH::clk1x_i	Module BUFH [generate]
BUFR::clk1x_i	Module BUFR [generate]
BUFMR::clk1x_i	Module BUFMR [generate]
BUFIO::clk1x_i	Module BUFIO [generate]
BUFG::clk2x_i	Module BUFG [generate]
BUFH::clk2x_i	Module BUFH [generate]
BUFR::clk2x_i	Module BUFR [generate]
BUFMR::clk2x_i	Module BUFMR [generate]
BUFIO::clk2x_i	Module BUFIO [generate]
pll_base::pll_base_i	Module pll_base

Detailed Description

Definition at line 41 of file dual_clock_source.v.

Member Data Documentation

CLKIN_PERIOD 20

Parameter

Definition at line 42 of file dual_clock_source.v.

DIVCLK_DIVIDE 1

Parameter

Definition at line 45 of file dual_clock_source.v.

CLKFBOUT_MULT 20

Parameter

Definition at line 46 of file dual_clock_source.v.

CLKOUT_DIV_CLK1X 10

Parameter

Definition at line 47 of file dual_clock_source.v.

CLKOUT_DIV_CLK2X 5

Parameter

Definition at line 48 of file dual_clock_source.v.

PHASE_CLK2X 0 . 000

Parameter

Definition at line 49 of file dual_clock_source.v.

BUF_CLK1X "BUFG "

Parameter

Definition at line 50 of file dual_clock_source.v.

BUF_CLK2X "BUFG "

Parameter

Definition at line 51 of file dual_clock_source.v.

rst

Input

Definition at line 53 of file dual_clock_source.v.

clk_in

Input

Definition at line 54 of file dual_clock_source.v.

pwrdwn

Input

Definition at line 55 of file dual_clock_source.v.

clk1x

Output

Definition at line 56 of file dual_clock_source.v.

clk2x

Output

Definition at line 57 of file dual_clock_source.v.

locked

Output

Definition at line 58 of file dual_clock_source.v.

clkfb

Signal

Definition at line 60 of file dual_clock_source.v.

clk1x_pre

Signal

Definition at line 60 of file dual_clock_source.v.

clk2x_pre

Signal

Definition at line 60 of file dual_clock_source.v.

BUFG clk1x_i

Module Instance

Definition at line 62 of file dual_clock_source.v.

BUFG clk2x_i

Module Instance

Definition at line 71 of file dual_clock_source.v.

BUFH clk1x_i

Module Instance

Definition at line 63 of file dual_clock_source.v.

BUFH clk2x_i

Module Instance

Definition at line 72 of file dual_clock_source.v.

BUFIO clk1x_i

Module Instance

Definition at line 66 of file dual_clock_source.v.

BUFIO clk2x_i

Module Instance

Definition at line 75 of file dual_clock_source.v.

BUFMR clk1x_i

Module Instance

Definition at line 65 of file dual_clock_source.v.

BUFMR clk2x_i

Module Instance

Definition at line 74 of file dual_clock_source.v.

BUFR clk1x_i

Module Instance

Definition at line 64 of file dual_clock_source.v.

BUFR clk2x_i

Module Instance

Definition at line 73 of file dual_clock_source.v.

GENERATE [61]

GENERATE

Definition at line 61 of file dual_clock_source.v.

GENERATE [70]

GENERATE

Definition at line 70 of file dual_clock_source.v.

pll_base pll_base_i

Module Instance

Definition at line 79 of file dual_clock_source.v.

---

The documentation for this Module was generated from the following files:

• util_modules/dual_clock_source.v