Public Attributes

Inputs
xclk
mrst
xrst
hrst
mclk
cmd_ad	[ 7 : 0 ]
cmd_stb
status_start
xfer_reset_page_rd	[ 3 : 0 ]
buf_wpage_nxt	[ 3 : 0 ]
buf_we	[ 3 : 0 ]
buf_din	[ 255 : 0 ]
page_ready	[ 3 : 0 ]
line_unfinished_src	[ 4 FRAME_HEIGHT_BITS* - 1 : 0 ]**
frame_number_src	[ 4 LAST_FRAME_BITS* - 1 : 0 ]**
frame_done_src	[ 3 : 0 ]
line_unfinished_dst	[ 4 FRAME_HEIGHT_BITS* - 1 : 0 ]**
frame_number_dst	[ 4 LAST_FRAME_BITS* - 1 : 0 ]**
frame_done_dst	[ 3 : 0 ]
ts_pre_stb	[ 3 : 0 ]
ts_data	[ 31 : 0 ]
vsync_late	[ 3 : 0 ]
frame_num_compressed	*[ 4 NUM_FRAME_BITS- 1 : 0 ]**
hclk
afi0_awready
afi0_wready
afi0_bvalid
afi0_bid	[ 5 : 0 ]
afi0_bresp	[ 1 : 0 ]
afi0_wcount	[ 7 : 0 ]
afi0_wacount	[ 5 : 0 ]
afi1_awready
afi1_wready
afi1_bvalid
afi1_bid	[ 5 : 0 ]
afi1_bresp	[ 1 : 0 ]
afi1_wcount	[ 7 : 0 ]
afi1_wacount	[ 5 : 0 ]
debug_sl
debug_di

Outputs
status_ad	[ 7 : 0 ]
status_rq
cmprs_irq	[ 3 : 0 ]
next_page	[ 3 : 0 ]
frame_start_dst	[ 3 : 0 ]
suspend	[ 3 : 0 ]
frame_number_finished	[ 4 LAST_FRAME_BITS* - 1 : 0 ]**
eof_written_mclk	[ 3 : 0 ]
stuffer_done_mclk	[ 3 : 0 ]
afi0_awaddr	[ 31 : 0 ]
afi0_awvalid
afi0_awid	[ 5 : 0 ]
afi0_awlock	[ 1 : 0 ]
afi0_awcache	[ 3 : 0 ]
afi0_awprot	[ 2 : 0 ]
afi0_awlen	[ 3 : 0 ]
afi0_awsize	[ 1 : 0 ]
afi0_awburst	[ 1 : 0 ]
afi0_awqos	[ 3 : 0 ]
afi0_wdata	[ 63 : 0 ]
afi0_wvalid
afi0_wid	[ 5 : 0 ]
afi0_wlast
afi0_wstrb	[ 7 : 0 ]
afi0_bready
afi0_wrissuecap1en
afi1_clk
afi1_awaddr	[ 31 : 0 ]
afi1_awvalid
afi1_awid	[ 5 : 0 ]
afi1_awlock	[ 1 : 0 ]
afi1_awcache	[ 3 : 0 ]
afi1_awprot	[ 2 : 0 ]
afi1_awlen	[ 3 : 0 ]
afi1_awsize	[ 1 : 0 ]
afi1_awburst	[ 1 : 0 ]
afi1_awqos	[ 3 : 0 ]
afi1_wdata	[ 63 : 0 ]
afi1_wvalid
afi1_wid	[ 5 : 0 ]
afi1_wlast
afi1_wstrb	[ 7 : 0 ]
afi1_bready
afi1_wrissuecap1en
debug_do

Parameters
CMPRS_NUM_AFI_CHN	2
CMPRS_GROUP_ADDR	'h600
CMPRS_BASE_INC	'h10
CMPRS_AFIMUX_RADDR0	'h40
CMPRS_AFIMUX_RADDR1	'h50
CMPRS_AFIMUX_MASK	'h7f0
CMPRS_STATUS_REG_BASE	'h10
CMPRS_HIFREQ_REG_BASE	'h14
CMPRS_AFIMUX_REG_ADDR0	'h18
CMPRS_AFIMUX_REG_ADDR1	'h1c
CMPRS_STATUS_REG_INC	1
CMPRS_HIFREQ_REG_INC	1
CMPRS_MASK	'h7f8
CMPRS_CONTROL_REG	0
CMPRS_STATUS_CNTRL	1
CMPRS_FORMAT	2
CMPRS_COLOR_SATURATION	3
CMPRS_CORING_MODE	4
CMPRS_INTERRUPTS	5
CMPRS_TABLES	6
TABLE_QUANTIZATION_INDEX	0
TABLE_CORING_INDEX	1
TABLE_FOCUS_INDEX	2
TABLE_HUFFMAN_INDEX	3
FRAME_HEIGHT_BITS	16
LAST_FRAME_BITS	16
CMPRS_CBIT_RUN	2
CMPRS_CBIT_RUN_BITS	2
CMPRS_CBIT_QBANK	6
CMPRS_CBIT_QBANK_BITS	3
CMPRS_CBIT_DCSUB	8
CMPRS_CBIT_DCSUB_BITS	1
CMPRS_CBIT_CMODE	13
CMPRS_CBIT_CMODE_BITS	4
CMPRS_CBIT_FRAMES	15
CMPRS_CBIT_FRAMES_BITS	1
CMPRS_CBIT_BAYER	20
CMPRS_CBIT_BAYER_BITS	2
CMPRS_CBIT_FOCUS	23
CMPRS_CBIT_FOCUS_BITS	2
CMPRS_CBIT_RUN_RST	2 'h0
CMPRS_CBIT_RUN_STANDALONE	2 'h2
CMPRS_CBIT_RUN_ENABLE	2 'h3
CMPRS_CBIT_CMODE_JPEG18	4 'h0
CMPRS_CBIT_CMODE_MONO6	4 'h1
CMPRS_CBIT_CMODE_JP46	4 'h2
CMPRS_CBIT_CMODE_JP46DC	4 'h3
CMPRS_CBIT_CMODE_JPEG20	4 'h4
CMPRS_CBIT_CMODE_JP4	4 'h5
CMPRS_CBIT_CMODE_JP4DC	4 'h6
CMPRS_CBIT_CMODE_JP4DIFF	4 'h7
CMPRS_CBIT_CMODE_JP4DIFFHDR	4 'h8
CMPRS_CBIT_CMODE_JP4DIFFDIV2	4 'h9
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2	4 'ha
CMPRS_CBIT_CMODE_MONO1	4 'hb
CMPRS_CBIT_CMODE_MONO4	4 'he
CMPRS_CBIT_FRAMES_SINGLE	0
CMPRS_COLOR18	0
CMPRS_COLOR20	1
CMPRS_MONO16	2
CMPRS_JP4	3
CMPRS_JP4DIFF	4
CMPRS_MONO8	7
CMPRS_FRMT_MBCM1	0
CMPRS_FRMT_MBCM1_BITS	13
CMPRS_FRMT_MBRM1	13
CMPRS_FRMT_MBRM1_BITS	13
CMPRS_FRMT_LMARG	26
CMPRS_FRMT_LMARG_BITS	5
CMPRS_CSAT_CB	0
CMPRS_CSAT_CB_BITS	10
CMPRS_CSAT_CR	12
CMPRS_CSAT_CR_BITS	10
CMPRS_CORING_BITS	3
CMPRS_TIMEOUT_BITS	12
CMPRS_TIMEOUT	1000
CMPRS_AFIMUX_EN	'h0
CMPRS_AFIMUX_RST	'h1
CMPRS_AFIMUX_MODE	'h2
CMPRS_AFIMUX_STATUS_CNTRL	'h4
CMPRS_AFIMUX_SA_LEN	'h8
CMPRS_AFIMUX_WIDTH	26
CMPRS_AFIMUX_CYCBITS	3
AFI_MUX_BUF_LATENCY	4 'd2
1931
1932
DEBUG_RING_LENGTH	5 + ((CMPRS_NUM_AFI_CHN > 1 )?1: 0

GENERATE
GENERATE [335]
GENERATE [476]

Signals
wire[DEBUG_RING_LENGTH : 0 ]	debug_ring
wire[ 47 : 0 ]	status_ad_mux
wire[ 5 : 0 ]	status_rq_mux
wire[ 5 : 0 ]	status_start_mux
wire[ 3 : 0 ]	fifo_rst
wire[ 3 : 0 ]	fifo_ren
wire[ 255 : 0 ]	fifo_rdata
wire[ 3 : 0 ]	fifo_eof
wire[ 3 : 0 ]	eof_written
wire[ 3 : 0 ]	fifo_flush
wire[ 3 : 0 ]	flush_hclk
wire[ 31 : 0 ]	fifo_count

Module Instances
status_router8::status_router8_i	Module status_router8
jp_channel::jp_channel_i	Module jp_channel [generate]
cmprs_afi_mux::cmprs_afi0_mux_i	Module cmprs_afi_mux [generate]
cmprs_afi_mux::cmprs_afi1_mux_i	Module cmprs_afi_mux [generate]