Static Public Member Functions

Always Constructs
ALWAYS_4	( mclk )
ALWAYS_5	( hclk )
ALWAYS_6	( hclk )

Public Attributes

Inputs
mclk
hclk
mrst
hrst
cmd_ad	[ 7 : 0 ]
cmd_stb
status_start
fifo_rdata0	[ 63 : 0 ]
pre_flush0
fifo_flush0
fifo_count0	[ 7 : 0 ]
fifo_rdata1	[ 63 : 0 ]
pre_flush1
fifo_flush1
fifo_count1	[ 7 : 0 ]
fifo_rdata2	[ 63 : 0 ]
pre_flush2
fifo_flush2
fifo_count2	[ 7 : 0 ]
fifo_rdata3	[ 63 : 0 ]
pre_flush3
fifo_flush3
fifo_count3	[ 7 : 0 ]
afi_awready
afi_wready
afi_bvalid
afi_bid	[ 5 : 0 ]
afi_bresp	[ 1 : 0 ]
afi_wcount	[ 7 : 0 ]
afi_wacount	[ 5 : 0 ]
debug_sl
debug_di

Outputs
status_ad	[ 7 : 0 ]
status_rq
fifo_rst0
fifo_ren0
eof_written0
fifo_rst1
fifo_ren1
eof_written1
fifo_rst2
fifo_ren2
eof_written2
fifo_rst3
fifo_ren3
eof_written3
afi_awaddr	[ 31 : 0 ]
afi_awvalid
afi_awid	[ 5 : 0 ]
afi_awlock	[ 1 : 0 ]
afi_awcache	[ 3 : 0 ]
afi_awprot	[ 2 : 0 ]
afi_awlen	reg [ 3 : 0 ]
afi_awsize	[ 1 : 0 ]
afi_awburst	[ 1 : 0 ]
afi_awqos	[ 3 : 0 ]
afi_wdata	[ 63 : 0 ]
afi_wvalid
afi_wid	[ 5 : 0 ]
afi_wlast
afi_wstrb	[ 7 : 0 ]
afi_bready
afi_wrissuecap1en
debug_do

Parameters
CMPRS_AFIMUX_ADDR	'h140
CMPRS_AFIMUX_MASK	'h7f0
CMPRS_AFIMUX_EN	'h0
CMPRS_AFIMUX_RST	'h1
CMPRS_AFIMUX_MODE	'h2
CMPRS_AFIMUX_STATUS_CNTRL	'h4
CMPRS_AFIMUX_SA_LEN	'h8
CMPRS_AFIMUX_STATUS_REG_ADDR	'h20
CMPRS_AFIMUX_WIDTH	26
CMPRS_AFIMUX_CYCBITS	3
123
124
AFI_MUX_BUF_LATENCYM1	[ 3 : 0 ] AFI_MUX_BUF_LATENCY - 1

Signals
reg	en
reg	en_d
wire	en_nrst
reg[ 3 : 0 ]	en_chn
wire[ 31 : 0 ]	cmd_data
wire[ 3 : 0 ]	cmd_a
wire	cmd_we
wire	cmd_we_status_w
wire	cmd_we_mode_w
wire	cmd_we_sa_len_w
wire	cmd_we_en_w
wire	cmd_we_rst_w
reg[ 26 : 0 ]	sa_len_d
reg[ 2 : 0 ]	sa_len_wa
reg[ 3 : 0 ]	rst_mclk
reg[ 9 : 0 ]	en_mclk
wire	sa_len_we
wire	en_we
wire	en_rst
wire[ 3 : 0 ]	fifo_flush
wire[ 3 : 0 ]	pre_flush
reg[ 3 : 0 ]	ren_suspend_flush
reg[ 1 : 0 ]	cur_chn
reg[ 31 : 0 ]	left_to_eof
reg[ 3 : 0 ]	fifo_flush_d
reg[ 3 : 0 ]	eof_stb
reg[ 35 : 0 ]	counts_corr0
reg[ 17 : 0 ]	counts_corr1
reg[ 8 : 0 ]	counts_corr2
reg[ 1 : 0 ]	winner1
reg[ 1 : 0 ]	winner2
wire[ 1 : 0 ]	pre_winner2_w
wire[ 7 : 0 ]	fifo_count0_m1
wire[ 7 : 0 ]	fifo_count1_m1
wire[ 7 : 0 ]	fifo_count2_m1
wire[ 7 : 0 ]	fifo_count3_m1
wire	need_to_bother
reg	ready_to_start
reg[ 3 : 0 ]	busy
wire	done_burst_w
wire	pre_busy_w
reg	first_busy
reg[ 3 : 0 ]	pend_last
reg	last_burst_in_frame
reg[ 3 : 0 ]	wleft
wire[ 1 : 0 ]	pre_chunk_inc_m1
reg[ 3 : 0 ]	reset_pointers
wire	ptr_resetting
wire[ 26 : 0 ]	chunk_addr
reg[ 1 : 0 ]	awvalid
reg	wvalid
reg	wlast
reg[ 63 : 0 ]	wdata
wire	wdata_en
wire[ 1 : 0 ]	wdata_sel
reg[ 3 : 0 ]	fifo_ren
wire[ 26 : 0 ]	chunk_ptr_rd
wire[ 3 : 0 ]	chunk_ptr_ra
wire[ 7 : 0 ]	items_left
reg[ 5 : 0 ]	afi_awid_r
wire[ 2 : 0 ]	max_wlen
wire[ 1 : 0 ]	want_wleft32
wire	rollover_limited_w
wire	afi_wvalid_w
wire[ 53 : 0 ]	chunk_ptr_rd01

Module Instances
debug_slave::debug_slave_i	Module debug_slave
dly_16::afi_wx_i	Module dly_16
dly_16::afi_wdata_i	Module dly_16
cmd_deser::cmd_deser_32bit_i	Module cmd_deser
cmprs_afi_mux_ptr::cmprs_afi_mux_ptr_i	Module cmprs_afi_mux_ptr
cmprs_afi_mux_ptr_wresp::cmprs_afi_mux_ptr_wresp_i	Module cmprs_afi_mux_ptr_wresp
cmprs_afi_mux_status::cmprs_afi_mux_status_i	Module cmprs_afi_mux_status
pulse_cross_clock::sa_len_we_i	Module pulse_cross_clock
pulse_cross_clock::en_we_i	Module pulse_cross_clock
pulse_cross_clock::en_rst_i	Module pulse_cross_clock