Static Public Member Functions

Always Constructs
ALWAYS_442	( mclk )
ALWAYS_443	( pclk )
ALWAYS_444	( pclk )
ALWAYS_445	( pclk )
ALWAYS_446	( pclk )

Public Attributes

Inputs
mclk
mrst
cmd_ad	[ 7 : 0 ]
cmd_stb
pclk
prst
gpio_in	[ 9 : 0 ]
frsync_chn0
frsync_chn1
frsync_chn2
frsync_chn3
ts_snd_stb_chn0
ts_snd_data_chn0	[ 7 : 0 ]
ts_snd_stb_chn1
ts_snd_data_chn1	[ 7 : 0 ]
ts_snd_stb_chn2
ts_snd_data_chn2	[ 7 : 0 ]
ts_snd_stb_chn3
ts_snd_data_chn3	[ 7 : 0 ]

Outputs
gpio_out	[ 9 : 0 ]
gpio_out_en	[ 9 : 0 ]
triggered_mode
trig_chn0
trig_chn1
trig_chn2
trig_chn3
ts_snap_mclk_chn0
ts_snap_mclk_chn1
ts_snap_mclk_chn2
ts_snap_mclk_chn3
ts_rcv_stb_chn0
ts_rcv_data_chn0	[ 7 : 0 ]
ts_rcv_stb_chn1
ts_rcv_data_chn1	[ 7 : 0 ]
ts_rcv_stb_chn2
ts_rcv_data_chn2	[ 7 : 0 ]
ts_rcv_stb_chn3
ts_rcv_data_chn3	[ 7 : 0 ]

Parameters
CAMSYNC_ADDR	'h160
CAMSYNC_MASK	'h7f8
CAMSYNC_MODE	'h0
CAMSYNC_TRIG_SRC	'h1
CAMSYNC_TRIG_DST	'h2
CAMSYNC_TRIG_PERIOD	'h3
CAMSYNC_TRIG_DELAY0	'h4
CAMSYNC_TRIG_DELAY1	'h5
CAMSYNC_TRIG_DELAY2	'h6
CAMSYNC_TRIG_DELAY3	'h7
CAMSYNC_EN_BIT	'h0
CAMSYNC_SNDEN_BIT	'h2
CAMSYNC_EXTERNAL_BIT	'h4
CAMSYNC_TRIGGERED_BIT	'h6
CAMSYNC_MASTER_BIT	'h9
CAMSYNC_CHN_EN_BIT	'he
CAMSYNC_PRE_MAGIC	6 'b110100
CAMSYNC_POST_MAGIC	6 'b001101

Signals
reg	en
wire	en_pclk
wire	eprst
reg	ts_snd_en
reg	ts_external
reg	triggered_mode_r
reg[ 31 : 0 ]	ts_snd_sec
reg[ 19 : 0 ]	ts_snd_usec
wire[ 31 : 0 ]	ts_snd_sec_chn0
wire[ 19 : 0 ]	ts_snd_usec_chn0
reg[ 31 : 0 ]	ts_rcv_sec_chn0
reg[ 19 : 0 ]	ts_rcv_usec_chn0
wire[ 3 : 0 ]	ts_stb
wire[ 31 : 0 ]	ts_snd_sec_chn1
wire[ 19 : 0 ]	ts_snd_usec_chn1
reg[ 31 : 0 ]	ts_rcv_sec_chn1
reg[ 19 : 0 ]	ts_rcv_usec_chn1
wire[ 31 : 0 ]	ts_snd_sec_chn2
wire[ 19 : 0 ]	ts_snd_usec_chn2
reg[ 31 : 0 ]	ts_rcv_sec_chn2
reg[ 19 : 0 ]	ts_rcv_usec_chn2
wire[ 31 : 0 ]	ts_snd_sec_chn3
wire[ 19 : 0 ]	ts_snd_usec_chn3
reg[ 31 : 0 ]	ts_rcv_sec_chn3
reg[ 19 : 0 ]	ts_rcv_usec_chn3
wire[ 2 : 0 ]	cmd_a
wire[ 31 : 0 ]	cmd_data
wire	cmd_we
wire	set_mode_reg_w
wire	set_trig_src_w
wire	set_trig_delay0_w
wire	set_trig_delay1_w
wire	set_trig_delay2_w
wire	set_trig_delay3_w
wire	set_trig_dst_w
wire	set_trig_period_w
wire[ 9 : 0 ]	pre_input_use
wire[ 9 : 0 ]	pre_input_pattern
reg	high_zero
reg[ 9 : 0 ]	input_use
reg[ 9 : 0 ]	input_pattern
reg[ 9 : 0 ]	gpio_out_en_r
reg	pre_input_use_intern
reg	input_use_intern
reg[ 31 : 0 ]	input_dly_chn0
reg[ 31 : 0 ]	input_dly_chn1
reg[ 31 : 0 ]	input_dly_chn2
reg[ 31 : 0 ]	input_dly_chn3
reg[ 3 : 0 ]	chn_en
reg[ 1 : 0 ]	master_chn
reg[ 9 : 0 ]	gpio_active
reg	testmode
reg	outsync
reg	out_data
reg[ 31 : 0 ]	repeat_period
reg	start
reg	start_d
reg	rep_en
reg	start_en
wire	start_to_pclk
reg[ 2 : 0 ]	start_pclk
reg[ 31 : 0 ]	restart_cntr
reg[ 1 : 0 ]	restart_cntr_run
wire	restart
reg	trigger_condition
reg	trigger_condition_d
reg	trigger_condition_filtered
reg[ 6 : 0 ]	trigger_filter_cntr
reg[ 3 : 0 ]	trig_r
wire[ 3 : 0 ]	trig_r_mclk
reg	start_dly
reg[ 31 : 0 ]	dly_cntr_chn0
reg[ 31 : 0 ]	dly_cntr_chn1
reg[ 31 : 0 ]	dly_cntr_chn2
reg[ 31 : 0 ]	dly_cntr_chn3
reg[ 3 : 0 ]	dly_cntr_run
reg[ 3 : 0 ]	dly_cntr_run_d
wire[ 3 : 0 ]	dly_cntr_end
wire	pre_start_out_pulse
reg	start_out_pulse
reg[ 31 : 0 ]	pre_period
reg[ 7 : 0 ]	bit_length
wire[ 7 : 0 ]	bit_length_plus1
reg[ 7 : 0 ]	bit_length_short
wire	pre_start0
reg	start0
wire	pre_set_bit
reg	set_bit
wire	pre_set_period
reg	set_period
wire	start_late
reg[ 31 : 0 ]	sr_snd_first
reg[ 31 : 0 ]	sr_snd_second
reg[ 31 : 0 ]	sr_rcv_first
reg[ 31 : 0 ]	sr_rcv_second
reg[ 7 : 0 ]	bit_snd_duration
reg[ 5 : 0 ]	bit_snd_counter
reg[ 7 : 0 ]	bit_rcv_duration
reg	bit_rcv_duration_zero
reg[ 6 : 0 ]	bit_rcv_counter
reg	bit_snd_duration_zero
reg	ts_snd_en_pclk
reg	rcv_run_or_deaf
wire	rcv_run
reg	rcv_run_d
reg	rcv_done_rq
reg	rcv_done_rq_d
reg	rcv_done
wire	rcv_done_mclk
wire	pre_rcv_error
reg	rcv_error
reg	ts_external_pclk
reg	triggered_mode_pclk
wire[ 3 : 0 ]	local_got
wire[ 3 : 0 ]	local_got_pclk
wire[ 3 : 0 ]	frame_sync
reg[ 3 : 0 ]	ts_snap_triggered
wire[ 3 : 0 ]	ts_snap_triggered_mclk
wire[ 9 : 0 ]	input_mask
wire[ 9 : 0 ]	input_use_w
wire[ 9 : 0 ]	input_pattern_w
wire[ 9 : 0 ]	pre_gpio_out_en
wire[ 9 : 0 ]	pre_gpio_active
wire[ 9 : 0 ]	output_mask
wire[ 9 : 0 ]	gpio_out_en_w
wire[ 9 : 0 ]	gpio_active_w

Module Instances
cmd_deser::cmd_deser_32bit_i	Module cmd_deser
timestamp_to_parallel::timestamp_to_parallel0_i	Module timestamp_to_parallel
timestamp_to_parallel::timestamp_to_parallel1_i	Module timestamp_to_parallel
timestamp_to_parallel::timestamp_to_parallel2_i	Module timestamp_to_parallel
timestamp_to_parallel::timestamp_to_parallel3_i	Module timestamp_to_parallel
timestamp_to_serial::timestamp_to_serial0_i	Module timestamp_to_serial
timestamp_to_serial::timestamp_to_serial1_i	Module timestamp_to_serial
timestamp_to_serial::timestamp_to_serial2_i	Module timestamp_to_serial
timestamp_to_serial::timestamp_to_serial3_i	Module timestamp_to_serial
level_cross_clocks::level_cross_clocks_en_pclki	Module level_cross_clocks
pulse_cross_clock::i_start_to_pclk	Module pulse_cross_clock
pulse_cross_clock::i_ts_snap_mclk0	Module pulse_cross_clock
pulse_cross_clock::i_ts_snap_mclk1	Module pulse_cross_clock
pulse_cross_clock::i_ts_snap_mclk2	Module pulse_cross_clock
pulse_cross_clock::i_ts_snap_mclk3	Module pulse_cross_clock
pulse_cross_clock::i_rcv_done_mclk	Module pulse_cross_clock
pulse_cross_clock::i_local_got_pclk0	Module pulse_cross_clock
pulse_cross_clock::i_local_got_pclk1	Module pulse_cross_clock
pulse_cross_clock::i_local_got_pclk2	Module pulse_cross_clock
pulse_cross_clock::i_local_got_pclk3	Module pulse_cross_clock
pulse_cross_clock::i_trig_r_mclk0	Module pulse_cross_clock
pulse_cross_clock::i_trig_r_mclk1	Module pulse_cross_clock
pulse_cross_clock::i_trig_r_mclk2	Module pulse_cross_clock
pulse_cross_clock::i_trig_r_mclk3	Module pulse_cross_clock