46 parameter CONTROL_ADDR =
'h0000,
// AXI write address of control write registers 51 input mrst,
// @posedge mclk - sync reset 52 input arst,
// @posedge axi_clk - sync reset 57 input ad_stb,
// low address output strobe (and parallel A/D) 60 input axird_start_burst,
// start of read burst, valid pre_araddr, save externally to control ext. dev_ready multiplexer 62 input axird_ren,
// .ren(bram_reg_re_w) , // read port enable 63 // input axird_regen, //==axird_ren?? - remove? .regen(bram_reg_re_w), // output register enable 64 output [
31:
0]
axird_rdata,
// combinatorial multiplexed (add external register layer, modify axibram_read?) .data_out(rdata[31:0]), // data out 65 output axird_selected // axird_rdata contains cvalid data from this module, vcalid next after axird_start_burst
10207waddrreg[CONTROL_RBACK_DEPTH-1:0]
10187CONTROL_RBACK_DEPTH11
10190CONTROL_RBACK_ADDR'h0000
[AXI_WR_ADDR_BITS-1:0] 10196par_waddr
[CONTROL_RBACK_DEPTH-1:0] 10201axird_raddr
[AXI_RD_ADDR_BITS-1:0] 10199axird_pre_araddr
10191CONTROL_RBACK_ADDR_MASK'h3800
10216axi_rback_rdata_rreg[31:0]
10215axi_rback_rdatareg[31:0]
[0:DATA_2DEPTH] 10206ramreg[31:0]
integer 10205DATA_2DEPTH(1<<CONTROL_RBACK_DEPTH)-1
10189CONTROL_ADDR_MASK'h3800