47 TODO Comments from cmd_encod_tiled_rd, update 48 Minimal ACTIVATE period =4 Tcm or 10ns, so maximal no-miss rate is Tck=1.25 ns (800 MHz) 49 Minimal window of 4 ACTIVATE pulses - 16 Tck or 40 (40 ns), so one ACTIVATE per 8 Tck is still OK down to 1.25 ns 50 Reads are in 16-byte colums: 1 8-burst (16 bytes) in a row, then next row, bank inc first. Then (if needed) - next column 51 Number of rows should be >=5 (4 now for tCK=2.5ns to meet tRP (precharge to activate) of the same bank (tRP=13ns) 52 Can read less if just one column 53 TODO: Maybe allow less rows with different sequence (no autoprecharge/no activate?) Will not work if row crosses page boundary 57 1: Most tile heights cause timing violation. Valid height mod 8 can be 0,6,7 (1,2,3,4,5 - invalid- wrong - that was for tile16 mode) 58 2: With option "keep_open" there should be no page boundary crossings, caller only checks the first line, and if window full width 59 is not multiple of CAS page, page crossings can appear on other than first line (fix caller to use largest common divider of page and 60 frame full width? Seems easy to fix 67 parameter CMD_DONE_BIT=
10,
// VDT BUG: CMD_DONE_BIT is used in a function call parameter! 73 // programming interface 78 //(for compatibility with cmd_encod_tiled, LSB will be ignored) 80 input [
5:
0]
num_cols_in_m1,
// number of 16-pixel columns to read (rows first, then columns) - 1 83 input start,
// start generating commands 84 output reg [
31:
0]
enc_cmd,
// encoded command 85 output reg enc_wr,
// write encoded command 97 localparam ENC_CMD_SHIFT=
6;
// [7:6] - command: 0 -= NOP, 1 - WRITE, 2 - PRECHARGE, 3 - ACTIVATE 107 localparam LOOP_FIRST=
6;
// address of the first word in a loop 108 localparam LOOP_LAST=
8;
// address of the last word in a loop 110 localparam CMD_NOP=
0;
// 3-bit normal memory RCW commands (positive logic) 117 reg [
2:
0]
bank;
// memory bank; 119 reg [
5:
0]
num_cols128_m1;
// number of r16-byte columns in a tile -1 (actually -2 with LSB==0) 125 // reg gen_run_d; // to output "done"? 135 reg [
FULL_ADDR_NUMBER-
4:
0]
top_rc;
// top combined row,column,bank burst address (excludes 3 CA LSBs), valid/modified @pre_act 138 wire pre_act;
//1 cycle before optional ACTIVATE 140 reg [
5:
0]
scan_row;
// current row in a tile (valid @pre_act) 141 reg [
5:
0]
scan_col;
// current 16-byte column in a tile (valid @pre_act) 159 // always @ (posedge clk) begin 160 // if (!gen_run) cut_buf_rd <= 0; 161 // else if ((gen_addr==(LOOP_LAST-1)) && !loop_continue) cut_buf_rd <= 1; 165 {
top_rc,
bank}:
// can not work if ACTIVATE is next after ACTIVATE in the last row (single-row tile) 172 assign rom_cmd=
rom_r[
ENC_CMD_SHIFT+:
2];
// & {enable_act,1'b1}; // disable bit 1 if activate is disabled (not the first column) 185 always @ (
posedge clk)
begin 247 // ROM-based (registered output) encoded sequence 248 always @ (
posedge clk)
begin 255 // 4'h4: rom_r <= (ENC_CMD_NOP << ENC_CMD_SHIFT) | (1 << ENC_BUF_RD) | (WSEL << ENC_SEL) | (1 << ENC_ODT) | (1 << ENC_DQ_DQS_EN); 274 always @ (
posedge clk)
begin 290 3'b0},
// [14:0] addr; // 15-bit row/column address 294 full_cmd[
2:
0],
// rcw; // RAS/CAS/WE, positive logic 296 1'b0,
// cke; // disable CKE 297 rom_r[
ENC_SEL],
// sel; // first/second half-cycle, other will be nop (cke+odt applicable to both) 298 rom_r[
ENC_DQ_DQS_EN],
// dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 299 rom_r[
ENC_DQ_DQS_EN],
// dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 301 1'b0,
// dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 302 1'b0,
// buf_wr; // connect to external buffer (but only if not paused) 303 // rom_r[ENC_BUF_RD] && !cut_buf_rd, // buf_rd; // connect to external buffer (but only if not paused) 304 rom_r[
ENC_BUF_RD],
// buf_rd; // connect to external buffer (but only if not paused) 305 rom_r[
ENC_NOP],
// nop; // add NOP after the current command, keep other data 307 else enc_cmd <=
func_encode_skip (
// encode pause 308 {{
CMD_PAUSE_BITS-
2{
1'b0}},
rom_skip[
1:
0]},
// skip; // number of extra cycles to skip (and keep all the other outputs) 309 pre_done,
// done // end of sequence **** 310 3'b0,
// bank (here OK to be any) 312 1'b0,
// cke; // disable CKE 313 rom_r[
ENC_SEL],
// sel; // first/second half-cycle, other will be nop (cke+odt applicable to both) 314 rom_r[
ENC_DQ_DQS_EN],
// dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 315 rom_r[
ENC_DQ_DQS_EN],
// dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 317 1'b0,
// dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 318 1'b0,
// buf_wr; // connect to external buffer (but only if not paused) 319 // rom_r[ENC_BUF_RD] && !cut_buf_rd, // buf_rd; // connect to external buffer (but only if not paused) 320 rom_r[
ENC_BUF_RD],
// buf_rd; // connect to external buffer (but only if not paused) 372 function [
31:
0]
func_encode_cmd;
373 input [
14:
0]
addr;
// 15-bit row/column address 374 input [
2:
0]
bank;
// bank (here OK to be any) 375 input [
2:
0]
rcw;
// RAS/CAS/WE, positive logic 376 input odt_en;
// enable ODT 377 input cke;
// disable CKE 378 input sel;
// first/second half-cycle, other will be nop (cke+odt applicable to both) 379 input dq_en;
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 380 input dqs_en;
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 381 input dqs_toggle;
// enable toggle DQS according to the pattern 382 input dci;
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 383 input buf_wr;
// connect to external buffer (but only if not paused) 384 input buf_rd;
// connect to external buffer (but only if not paused) 385 input nop;
// add NOP after the current command, keep other data 386 input buf_rst;
// connect to external buffer (but only if not paused) 389 addr[
14:
0],
// 15-bit row/column address 391 rcw[
2:
0],
// RAS/CAS/WE 392 odt_en,
// enable ODT 393 cke,
// may be optimized (removed from here)? 394 sel,
// first/second half-cycle, other will be nop (cke+odt applicable to both) 395 dq_en,
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 396 dqs_en,
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 397 dqs_toggle,
// enable toggle DQS according to the pattern 398 dci,
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 399 buf_wr,
// phy_buf_wr, // connect to external buffer (but only if not paused) 400 buf_rd,
// phy_buf_rd, // connect to external buffer (but only if not paused) 401 nop,
// add NOP after the current command, keep other data 402 buf_rst // Reserved for future use 407 function [
31:
0]
func_encode_skip;
408 input [
CMD_PAUSE_BITS-
1:
0]
skip;
// number of extra cycles to skip (and keep all the other outputs) 409 input done;
// end of sequence 410 input [
2:
0]
bank;
// bank (here OK to be any) 411 input odt_en;
// enable ODT 412 input cke;
// disable CKE 413 input sel;
// first/second half-cycle, other will be nop (cke+odt applicable to both) 414 input dq_en;
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 415 input dqs_en;
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 416 input dqs_toggle;
// enable toggle DQS according to the pattern 417 input dci;
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 418 input buf_wr;
// connect to external buffer (but only if not paused) 419 input buf_rd;
// connect to external buffer (but only if not paused) 420 input buf_rst;
// connect to external buffer (but only if not paused) 422 func_encode_skip=
func_encode_cmd (
424 bank[
2:
0],
// bank (here OK to be any) 425 3'b0,
// RAS/CAS/WE, positive logic 426 odt_en,
// enable ODT 428 sel,
// first/second half-cycle, other will be nop (cke+odt applicable to both) 429 dq_en,
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 430 dqs_en,
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 431 dqs_toggle,
// enable toggle DQS according to the pattern 432 dci,
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 433 buf_wr,
// connect to external buffer (but only if not paused) 434 buf_rd,
// connect to external buffer (but only if not paused) 4228colreg[COLADDR_NUMBER-4:0]
[ADDRESS_NUMBER-1:0] 4194start_row
4236gen_addrreg[ROM_DEPTH-1:0]
4205FULL_ADDR_NUMBERADDRESS_NUMBER+COLADDR_NUMBER
4251row_col_bankreg[FULL_ADDR_NUMBER-1:0]
4227rowreg[ADDRESS_NUMBER-1:0]
4232rowcol_increg[FRAME_WIDTH_BITS:0]
[COLADDR_NUMBER-4:0] 4195start_col
4242top_rcreg[FULL_ADDR_NUMBER-4:0]
4258row_col_bank_next_wwire[FULL_ADDR_NUMBER-1:0]
[FRAME_WIDTH_BITS:0] 4196rowcol_inc_in
4252col_bankwire[COLADDR_NUMBER-1:0]
4231num_cols128_m1reg[5:0]
4256next_rowcol_wwire[ADDRESS_NUMBER+COLADDR_NUMBER-4:0]
4237rom_rreg[ROM_WIDTH-1:0]