43 // parameter BASEADDR = 0, 46 parameter NUM_XFER_BITS=
6,
// number of bits to specify transfer length 48 parameter CMD_DONE_BIT=
10,
// VDT BUG: CMD_DONE_BIT is used in a function call parameter! 53 // programming interface 54 // input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 55 // input cmd_stb, // strobe (with first byte) for the command a/d 59 input [
NUM_XFER_BITS-
1:
0]
num128_in,
// number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) 61 input start,
// start generating commands 62 output reg [
31:
0]
enc_cmd,
// encoded command SuppressThisWarning VivadoSynthesis [Synth 8-3332] Sequential element cmd_encod_linear_rd.enc_cmd_reg[10:9,7:5,2] is unused and will be removed from module cmd_encod_linear_rd. 63 output reg enc_wr,
// write encoded command 69 // localparam ENC_BUF_PGNEXT= 0; 74 localparam ENC_CMD_SHIFT=
4;
// [5:4] - command: 0 -= NOP, 1 - READ, 2 - PRECHARGE, 3 - ACTIVATE 85 localparam CMD_NOP=
0;
// 3-bit normal memory RCW commands (positive logic) 91 reg [
COLADDR_NUMBER-
4:
0]
col;
// start memory column (3 LSBs should be 0?) // VDT BUG: col is used as a function call parameter! 92 reg [
2:
0]
bank;
// memory bank; 99 reg [
ROM_WIDTH-
1:
0]
rom_r;
// SuppressThisWarning VivadoSynthesis [Synth 8-3332] Sequential element cmd_encod_linear_rd.rom_r_reg[0] is unused and will be removed from module cmd_encod_linear_rd. 111 always @ (
posedge clk)
begin 119 /// else if ((gen_addr==(REPEAT_ADDR-1)) && (num128[NUM_XFER_BITS-1:1]==0)) gen_addr <= REPEAT_ADDR+1; // skip loop alltogeter 120 // AF 2015/09/12 : num128[NUM_XFER_BITS-1:0] == 0 for the full 64-bursts! 136 always @ (
posedge clk)
begin 141 // ROM-based (registered output) encoded sequence 142 always @ (
posedge clk)
begin 157 always @ (
posedge clk)
begin 168 {{
CMD_PAUSE_BITS-
2{
1'b0}},
rom_skip[
1:
0]},
// skip; // number of extra cycles to skip (and keep all the other outputs) 169 pre_done,
// done, // end of sequence 170 bank[
2:
0],
// bank (here OK to be any) 171 1'b0,
// odt_en; // enable ODT 172 1'b0,
// cke; // disable CKE 173 rom_r[
ENC_SEL],
// sel; // first/second half-cycle, other will be nop (cke+odt applicable to both) 174 1'b0,
// dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 175 1'b0,
// dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 176 1'b0,
// dqs_toggle; // enable toggle DQS according to the pattern 177 rom_r[
ENC_DCI],
// dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 178 rom_r[
ENC_BUF_WR],
// buf_wr; // connect to external buffer (but only if not paused) 179 1'b0,
// buf_rd; // connect to external buffer (but only if not paused) 181 else enc_cmd <=
func_encode_cmd (
// encode non-NOP command 185 bank[
2:
0],
// bank (here OK to be any) 186 full_cmd[
2:
0],
// rcw; // RAS/CAS/WE, positive logic 187 1'b0,
// odt_en; // enable ODT 188 1'b0,
// cke; // disable CKE 189 rom_r[
ENC_SEL],
// sel; // first/second half-cycle, other will be nop (cke+odt applicable to both) 190 1'b0,
// dq_en; // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 191 1'b0,
// dqs_en; // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 192 1'b0,
// dqs_toggle; // enable toggle DQS according to the pattern 193 rom_r[
ENC_DCI],
// dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 194 rom_r[
ENC_BUF_WR],
// buf_wr; // connect to external buffer (but only if not paused) 195 1'b0,
// buf_rd; // connect to external buffer (but only if not paused) 196 rom_r[
ENC_NOP],
// nop; // add NOP after the current command, keep other data 201 // move to include?/*! 202 * @file x393_mcontr_encode_cmd.vh
204 * @author Andrey Filippov
206 * @brief Functions used to encode memory controller sequences
208 * @copyright Copyright (c)
2015 Elphel, Inc.
212 * x393_mcontr_encode_cmd.vh is free software; you can redistribute it
and/
or modify
213 * it under the terms of the GNU General Public License as published by
214 * the Free Software Foundation, either version
3 of the License,
or 215 * (at your option) any later version.
217 * x393_mcontr_encode_cmd.vh is distributed in the hope that it will be useful,
218 * but WITHOUT ANY WARRANTY; without even the implied warranty of
219 * MERCHANTABILITY
or FITNESS
FOR A PARTICULAR PURPOSE. See the
220 * GNU General Public License
for more details.
222 * You should have received a copy of the GNU General Public License
223 * along with this program.
If not, see <http:
//www.gnu.org/licenses/> . 225 * Additional permission under GNU GPL version
3 section
7:
226 *
If you modify this Program,
or any covered work, by linking
or combining it
227 * with independent modules provided by the FPGA vendor only (this permission
228 * does
not extend to any
3-rd party modules,
"soft cores" or macros) under
229 * different license terms solely
for the purpose of generating binary
"bitstream" 230 * files
and/
or simulating the code, the copyright holders of this Program give
231 * you the right to distribute the covered work without those independent modules
232 * as long as the source code
for them is available from the FPGA vendor free of
233 * charge,
and there is no dependence on any encrypted modules
for simulating of
234 * the combined code. This permission applies to you
if the distributed code
235 * contains all the components
and scripts required to completely simulate it
236 * with at least one of the Free Software programs.
239 function [
31:
0] func_encode_cmd;
240 input [
14:
0] addr;
// 15-bit row/column address 241 input [
2:
0]
bank;
// bank (here OK to be any) 242 input [
2:
0] rcw;
// RAS/CAS/WE, positive logic 243 input odt_en;
// enable ODT 244 input cke;
// disable CKE 245 input sel;
// first/second half-cycle, other will be nop (cke+odt applicable to both) 246 input dq_en;
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 247 input dqs_en;
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 248 input dqs_toggle;
// enable toggle DQS according to the pattern 249 input dci;
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 250 input buf_wr;
// connect to external buffer (but only if not paused) 251 input buf_rd;
// connect to external buffer (but only if not paused) 252 input nop;
// add NOP after the current command, keep other data 253 input buf_rst;
// connect to external buffer (but only if not paused) 256 addr[
14:
0],
// 15-bit row/column address 258 rcw[
2:
0],
// RAS/CAS/WE 259 odt_en,
// enable ODT 260 cke,
// may be optimized (removed from here)? 261 sel,
// first/second half-cycle, other will be nop (cke+odt applicable to both) 262 dq_en,
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 263 dqs_en,
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 264 dqs_toggle,
// enable toggle DQS according to the pattern 265 dci,
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 266 buf_wr,
// phy_buf_wr, // connect to external buffer (but only if not paused) 267 buf_rd,
// phy_buf_rd, // connect to external buffer (but only if not paused) 268 nop,
// add NOP after the current command, keep other data 269 buf_rst
// Reserved for future use 274 function [
31:
0] func_encode_skip;
275 input [
CMD_PAUSE_BITS-
1:
0] skip;
// number of extra cycles to skip (and keep all the other outputs) 276 input done;
// end of sequence 277 input [
2:
0]
bank;
// bank (here OK to be any) 278 input odt_en;
// enable ODT 279 input cke;
// disable CKE 280 input sel;
// first/second half-cycle, other will be nop (cke+odt applicable to both) 281 input dq_en;
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 282 input dqs_en;
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 283 input dqs_toggle;
// enable toggle DQS according to the pattern 284 input dci;
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 285 input buf_wr;
// connect to external buffer (but only if not paused) 286 input buf_rd;
// connect to external buffer (but only if not paused) 287 input buf_rst;
// connect to external buffer (but only if not paused) 289 func_encode_skip= func_encode_cmd (
291 bank[
2:
0],
// bank (here OK to be any) 292 3'b0,
// RAS/CAS/WE, positive logic 293 odt_en,
// enable ODT 295 sel,
// first/second half-cycle, other will be nop (cke+odt applicable to both) 296 dq_en,
// enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0) 297 dqs_en,
// enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0) 298 dqs_toggle,
// enable toggle DQS according to the pattern 299 dci,
// DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0) 300 buf_wr,
// connect to external buffer (but only if not paused) 301 buf_rd,
// connect to external buffer (but only if not paused)
3986gen_addrreg[ROM_DEPTH-1:0]
3987rom_rreg[ROM_WIDTH-1:0]
3980rowreg[ADDRESS_NUMBER-1:0]
[NUM_XFER_BITS-1:0] 3955num128_in
3983num128reg[NUM_XFER_BITS-1:0]
[ADDRESS_NUMBER-1:0] 3953row_in
3981colreg[COLADDR_NUMBER-4:0]
[COLADDR_NUMBER-4:0] 3954start_col