42 input xclk,
// pixel clock, sync to incoming data 45 input [
31:
0]
din,
// input data, MSB aligned 46 input [
1:
0]
bytes_in,
// number of bytes, valid @ ds (0 means 4) 47 input in_stb,
// input data/bytes_in strobe 49 output reg [
31:
0]
d_out,
// output 32-bit data 50 output reg [
1:
0]
bytes_out,
// valid @dv(only), 0 means 4 bytes 51 output reg dv,
// output data valid 52 output reg flush_out // delayed flush in matching the data latency 59 // mask output for flushing 74 for (
i =
0;
i <
4;
i =
i+
1)
begin:
byte_fifo_block 92 reg cry_ff;
// 0xff was the last byte in the previous word 93 reg [
1:
0]
fifo_byte_pntr;
// byte pointer in fifo output, starting from MSB (0) 106 // folowing registers are combinatorial signals 107 reg sel3_w;
// select source for byte3 (MSB) from the barrel-shifted:0, it's own, 1 - zero (escape) 108 reg [
1:
0]
sel2_w;
// select source for byte2 from the barrel-shifted: 0, it's own, 1 - next higher byte, 3 - zero (escape) 109 reg [
1:
0]
sel1_w;
// select source for byte1 from the barrel-shifted: 0, it's own, 1 - next higher byte, 3 - zero (escape) 110 reg [
1:
0]
sel0_w;
// select source for byte0 (LSB) from the barrel-shifted: 0, it's own, 1 - next higher byte, 2 - two bytes higher, 113 reg [
3:
0]
bytes_rdy_w;
// data is available to generate an output word 115 reg [
1:
0]
num_zeros_w;
// number of escape zeros in the output word 116 reg [
3:
0]
fifo_re_mask_w;
// which fifo to read, bitmask (to be AND-ed with &bytes_rdy_w[3:0]} 206 // assign fifo_re = flush_pend[2]? fifo_nempty : (rdy_w ? fifo_re_mask_w : 4'b0); // when flushing read whatever is left 220 1'b1 :
d_out[
31:
24] <=
8'b0;
225 2'b11 :
d_out[
23:
16] <=
8'b0;
226 default :
d_out[
23:
16] <=
'bx;
231 2'b11 :
d_out[
15:
8] <=
8'b0;
232 default :
d_out[
15:
8] <=
'bx;
238 2'b11 :
d_out[
7:
0] <=
8'b0;
239 default :
d_out[
7:
0] <=
'bx;
[DATA_WIDTH-1:0] 10430data_in
fifo_same_clock_i fifo_same_clock[generate]
1310fifo_byte_pntrreg[1:0]
1313fifo_out_barrel_wwire[31:0]
1312fifo_nempty_barrel_wwire[3:0]
1322fifo_re_mask_wreg[3:0]
[DATA_WIDTH-1:0] 10431data_out
1311fifo_ff_barrel_wwire[3:0]
1308bytes_in_mask_wreg[3:0]
1305fifo_pre_outwire[31:0]