Collaboration diagram for link:

Static Public Member Functions

Always Constructs
ALWAYS_661	( clk )
ALWAYS_662	( clk )
ALWAYS_663	( clk )
ALWAYS_664	( clk )
ALWAYS_665	( clk )
ALWAYS_666	( clk )
ALWAYS_667	( clk )
ALWAYS_668	( clk )
ALWAYS_669	( clk )
ALWAYS_670	( clk )
ALWAYS_671	( clk )
ALWAYS_672	( clk )
ALWAYS_673	( clk )

Public Attributes

Inputs
rst	wire
clk	wire
data_in	wire [DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**
data_mask_in	wire [DATA_BYTE_WIDTH / 2 - 1 : 0 ]
data_last_in	wire
data_val_in	wire
data_busy_in	wire
frame_req	wire
incom_ack_good	wire
incom_ack_bad	wire
link_reset	wire
sync_escape_req	wire
incom_stop_req	wire
phy_ready	wire
phy_data_in	wire [DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**
phy_isk_in	wire [DATA_BYTE_WIDTH - 1 : 0 ]
phy_err_in	wire [DATA_BYTE_WIDTH - 1 : 0 ]

Outputs
data_strobe_out	wire
data_out	wire [DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**
data_mask_out	wire [DATA_BYTE_WIDTH / 2 - 1 : 0 ]
data_val_out	wire
data_last_out	wire
frame_busy	wire
frame_ack	wire
frame_rej	wire
frame_done_good	wire
frame_done_bad	wire
incom_start	wire
incom_done	wire
incom_invalidate	wire
incom_sync_escape	wire
sync_escape_ack	wire
link_established
link_bad_crc	reg
phy_data_out	wire [DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**
phy_isk_out	wire [DATA_BYTE_WIDTH - 1 : 0 ]
debug_out	[ 31 : 0 ]

Parameters
DATA_BYTE_WIDTH	4
15054
PRIM_NUM	16
CODE_DATA	0
CODE_CRC	1
CODE_SYNCP	2
CODE_ALIGNP	3
CODE_XRDYP	4
CODE_SOFP	5
CODE_HOLDAP	6
CODE_HOLDP	7
CODE_EOFP	8
CODE_WTRMP	9
CODE_RRDYP	10
CODE_IPP	11
CODE_DMATP	12
CODE_OKP	13
CODE_ERRP	14
CODE_CONTP	15
STATES_COUNT	23
PRIM_SYNCP_HI	[ 15 : 0 ] {3'd5 5 'd21 3 'd5 5 'd21}
PRIM_SYNCP_LO	[ 15 : 0 ] {3'd4 5 'd21 3 'd3 5 'd28}
PRIM_ALIGNP_HI	[ 15 : 0 ] {3'd3 5 'd27 3 'd2 5 'd10}
PRIM_ALIGNP_LO	[ 15 : 0 ] {3'd2 5 'd10 3 'd5 5 'd28}
PRIM_XRDYP_HI	[ 15 : 0 ] {3'd2 5 'd23 3 'd2 5 'd23}
PRIM_XRDYP_LO	[ 15 : 0 ] {3'd5 5 'd21 3 'd3 5 'd28}
PRIM_SOFP_HI	[ 15 : 0 ] {3'd1 5 'd23 3 'd1 5 'd23}
PRIM_SOFP_LO	[ 15 : 0 ] {3'd5 5 'd21 3 'd3 5 'd28}
PRIM_HOLDAP_HI	[ 15 : 0 ] {3'd4 5 'd21 3 'd4 5 'd21}
PRIM_HOLDAP_LO	[ 15 : 0 ] {3'd5 5 'd10 3 'd3 5 'd28}
PRIM_HOLDP_HI	[ 15 : 0 ] {3'd6 5 'd21 3 'd6 5 'd21}
PRIM_HOLDP_LO	[ 15 : 0 ] {3'd5 5 'd10 3 'd3 5 'd28}
PRIM_EOFP_HI	[ 15 : 0 ] {3'd6 5 'd21 3 'd6 5 'd21}
PRIM_EOFP_LO	[ 15 : 0 ] {3'd5 5 'd21 3 'd3 5 'd28}
PRIM_WTRMP_HI	[ 15 : 0 ] {3'd2 5 'd24 3 'd2 5 'd24}
PRIM_WTRMP_LO	[ 15 : 0 ] {3'd5 5 'd21 3 'd3 5 'd28}
PRIM_RRDYP_HI	[ 15 : 0 ] {3'd2 5 'd10 3 'd2 5 'd10}
PRIM_RRDYP_LO	[ 15 : 0 ] {3'd4 5 'd21 3 'd3 5 'd28}
PRIM_IPP_HI	[ 15 : 0 ] {3'd2 5 'd21 3 'd2 5 'd21}
PRIM_IPP_LO	[ 15 : 0 ] {3'd5 5 'd21 3 'd3 5 'd28}
PRIM_DMATP_HI	[ 15 : 0 ] {3'd1 5 'd22 3 'd1 5 'd22}
PRIM_DMATP_LO	[ 15 : 0 ] {3'd5 5 'd21 3 'd3 5 'd28}
PRIM_OKP_HI	[ 15 : 0 ] {3'd1 5 'd21 3 'd1 5 'd21}
PRIM_OKP_LO	[ 15 : 0 ] {3'd5 5 'd21 3 'd3 5 'd28}
PRIM_ERRP_HI	[ 15 : 0 ] {3'd2 5 'd22 3 'd2 5 'd22}
PRIM_ERRP_LO	[ 15 : 0 ] {3'd5 5 'd21 3 'd3 5 'd28}
PRIM_CONTP_HI	[ 15 : 0 ] {3'd4 5 'd25 3 'd4 5 'd25}
PRIM_CONTP_LO	[ 15 : 0 ] {3'd5 5 'd10 3 'd3 5 'd28}

GENERATE
GENERATE [521]

Signals
reg[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	phy_data_in_r
reg[DATA_BYTE_WIDTH - 1 : 0 ]	phy_isk_in_r
reg[DATA_BYTE_WIDTH - 1 : 0 ]	phy_err_in_r
reg[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	phy_data_in_r0
reg[DATA_BYTE_WIDTH - 1 : 0 ]	phy_isk_in_r0
reg[DATA_BYTE_WIDTH - 1 : 0 ]	phy_err_in_r0
reg[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	last_not_cont_di
reg	rcv_junk
wire	is_non_cont_non_align_p_w
wire	is_cont_p_w
wire	is_align_p_w
wire	frame_done
wire[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	scrambler_out
wire	dec_err
wire	crc_good
wire	crc_bad
wire[ 31 : 0 ]	crc_dword
wire[PRIM_NUM - 1 : 0 ]	rcvd_dword
wire	dword_val
wire	dword_val_na
wire	next_will_be_data
reg	data_txing_r
wire	data_txing
wire	state_idle
reg	state_sync_esc
reg	state_nocommerr
reg	state_nocomm
reg	state_align
reg	state_reset
reg	state_send_rdy
reg	state_send_sof
reg	state_send_data
reg	state_send_rhold
reg	state_send_shold
reg	state_send_crc
reg	state_send_eof
reg	state_wait
reg	state_rcvr_wait
reg	state_rcvr_rdy
reg	state_rcvr_data
reg	state_rcvr_rhold
reg	state_rcvr_shold
reg	state_rcvr_eof
reg	state_rcvr_goodcrc
reg	state_rcvr_goodend
reg	state_rcvr_badend
reg	incom_ack_good_pend
reg	incom_ack_bad_pend
wire	incom_ack_good_or_pend
wire	incom_ack_bad_or_pend
wire	set_sync_esc
wire	set_nocommerr
wire	set_nocomm
wire	set_align
wire	set_reset
wire	set_send_rdy
wire	set_send_sof
wire	set_send_data
wire	set_send_rhold
wire	set_send_shold
wire	set_send_crc
wire	set_send_eof
wire	set_wait
wire	set_rcvr_wait
wire	set_rcvr_rdy
wire	set_rcvr_data
wire	set_rcvr_rhold
wire	set_rcvr_shold
wire	set_rcvr_eof
wire	set_rcvr_goodcrc
wire	set_rcvr_goodend
wire	set_rcvr_badend
wire	clr_sync_esc
wire	clr_nocommerr
wire	clr_nocomm
wire	clr_align
wire	clr_reset
wire	clr_send_rdy
wire	clr_send_sof
wire	clr_send_data
wire	clr_send_rhold
wire	clr_send_shold
wire	clr_send_crc
wire	clr_send_eof
wire	clr_wait
wire	clr_rcvr_wait
wire	clr_rcvr_rdy
wire	clr_rcvr_data
wire	clr_rcvr_rhold
wire	clr_rcvr_shold
wire	clr_rcvr_eof
wire	clr_rcvr_goodcrc
wire	clr_rcvr_goodend
wire	clr_rcvr_badend
wire	got_escape
reg	sync_escape_req_r
reg	alignes_pair
reg[ 8 : 0 ]	alignes_timer
reg	alignes_pair_0
reg	incom_stop_f
[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	to_phy_data
reg[DATA_BYTE_WIDTH - 1 : 0 ]	to_phy_isk
wire[DATA_BYTE_WIDTH** * 8 - 1 : 0 ]**	prim_data [PRIM_NUM - 1 : 0 ]
wire[PRIM_NUM - 1 : 0 ]	select_prim
wire	inc_is_data
reg[ 31 : 0 ]	data_out_r
reg	data_val_out_r
reg[ 31 : 0 ]	data_out_rr
reg	data_val_out_rr
reg	data_held
wire	frame_rej_w
wire	incom_start_w
wire	incom_done_w
wire	incom_invalidate_w
reg	frame_rej_r
reg	incom_start_r
reg	incom_done_r
reg	incom_invalidate_r
wire[PRIM_NUM - 1 : 0 ]	rcvd_dword0
reg[PRIM_NUM - 1 : 0 ]	debug_rcvd_dword
reg	debug_first_error
reg	debug_first_alignp
reg	debug_first_syncp
reg	debug_first_nonsyncp
reg	debug_first_unknown
reg[ 19 : 0 ]	debug_to_first_err
reg[ 15 : 0 ]	debug_num_aligns
reg[ 15 : 0 ]	debug_num_syncs
reg[ 15 : 0 ]	debug_num_later_aligns
reg	other_prim_r
reg[ 15 : 0 ]	debug_num_other
reg[ 31 : 0 ]	debug_unknown_dword
wire	debug_is_sync_p_w
wire[STATES_COUNT - 1 : 0 ]	debug_states_concat
reg[ 4 : 0 ]	debug_states_encoded
reg[STATES_COUNT - 1 : 0 ]	debug_states_visited
reg[ 1 : 0 ]	debug_data_last_in_r
reg[ 1 : 0 ]	debug_alignes_pair_r
reg[ 1 : 0 ]	debug_state_send_data_r
reg[ 1 : 0 ]	debug_dword_val_na
reg[ 1 : 0 ]	debug_CODE_SYNCP
reg[ 1 : 0 ]	debug_set_send_crc
reg[ 1 : 0 ]	debug_data_val_in
reg[ 1 : 0 ]	debug_was_OK_ERR
reg	debug_was_wait
reg	debug_was_idle
reg	debug_was_ok_err
reg	debug_was_state_wait
reg	debug_was_frame_done
reg	debug_was_got_escape