axi_hp_clk Module Reference

Inheritance diagram for axi_hp_clk:

Collaboration diagram for axi_hp_clk:

Public Attributes

Inputs
rst
clk_in

Outputs
clk_axihp
locked_axihp

Parameters
CLKIN_PERIOD	20
CLKFBOUT_MULT_AXIHP	18
CLKFBOUT_DIV_AXIHP	6

Signals
wire	clkfb_axihp
wire	clk_axihp_pre

Module Instances
BUFG::clk_axihp_i	Module BUFG
pll_base::pll_base_i	Module pll_base

Detailed Description

Definition at line 41 of file axi_hp_clk.v.

Member Data Documentation

CLKIN_PERIOD 20

Parameter

Definition at line 42 of file axi_hp_clk.v.

CLKFBOUT_MULT_AXIHP 18

Parameter

Definition at line 43 of file axi_hp_clk.v.

CLKFBOUT_DIV_AXIHP 6

Parameter

Definition at line 44 of file axi_hp_clk.v.

rst

Input

Definition at line 46 of file axi_hp_clk.v.

clk_in

Input

Definition at line 47 of file axi_hp_clk.v.

clk_axihp

Output

Definition at line 48 of file axi_hp_clk.v.

locked_axihp

Output

Definition at line 49 of file axi_hp_clk.v.

clkfb_axihp

Signal

Definition at line 51 of file axi_hp_clk.v.

clk_axihp_pre

Signal

Definition at line 51 of file axi_hp_clk.v.

BUFG clk_axihp_i

Module Instance

Definition at line 52 of file axi_hp_clk.v.

pll_base pll_base_i

Module Instance

Definition at line 53 of file axi_hp_clk.v.

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The documentation for this Module was generated from the following files:

• util_modules/axi_hp_clk.v