os/linux-2.6-tag--devboard-R2_10-4/arch/cris/arch-v32/drivers/elphel/cxdma353.c

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/*!***************************************************************************
*! FILE NAME  : cxdma353.c
*! DESCRIPTION: Handling ETRAX DMA in Elphel model 353 camera
*! Copyright (C) 2002-2008 Elphel, Inc
*! -----------------------------------------------------------------------------**
*!
*!  This program is free software: you can redistribute it and/or modify
*!  it under the terms of the GNU General Public License as published by
*!  the Free Software Foundation, either version 3 of the License, or
*!  (at your option) any later version.
*!
*!  This program is distributed in the hope that it will be useful,
*!  but WITHOUT ANY WARRANTY; without even the implied warranty of
*!  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*!  GNU General Public License for more details.
*!
*!  You should have received a copy of the GNU General Public License
*!  along with this program.  If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!  $Log: cxdma353.c,v $
*!  Revision 1.1.1.1  2008/11/27 20:04:00  elphel
*!
*!
*!  Revision 1.12  2008/10/29 04:18:28  elphel
*!  v.8.0.alpha10 made a separate structure for global parameters (not related to particular frames in a frame queue)
*!
*!  Revision 1.11  2008/09/16 00:49:30  elphel
*!  snapshot
*!
*!  Revision 1.10  2008/09/12 00:23:58  elphel
*!  removed cc353.c, cc353.h
*!
*!  Revision 1.9  2008/09/11 01:05:31  elphel
*!  snapshot
*!
*!  Revision 1.8  2008/09/07 19:48:08  elphel
*!  snapshot
*!
*/

/****************** INCLUDE FILES SECTION ***********************************/


#include <linux/module.h>
#include <linux/mm.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/autoconf.h>
#include <linux/time.h>

#include <asm/system.h>
#include <asm/arch/memmap.h>
#include <asm/io.h>

#include <asm/arch/dma.h>
#include <asm/arch/hwregs/dma_defs.h>
#include <asm/arch/hwregs/dma.h>
#include <asm/arch/hwregs/reg_map.h>
#include <asm/arch/hwregs/bif_dma_defs.h>


#include <asm/irq.h>
#include <asm/atomic.h>

#include <asm/delay.h>
#include <asm/uaccess.h>
#include <asm/arch/cache.h>

#include <asm/elphel/c313a.h>

#include "fpgactrl.h"  // defines port_csp0_addr, port_csp4_addr 

#include "x3x3.h"
//#include "cc3x3.h"
#include "framepars.h"
#include "cxdma.h"
#include "sensor_common.h"
#include "circbuf.h"
#include "exif.h"

#if ELPHEL_DEBUG
 #define MD1(x) printk("%s:%d:",__FILE__,__LINE__);x
 #define MD12(x) printk("%s:%d:",__FILE__,__LINE__);x
  //#define MD12(x)
 #define MD13(x) printk("%s:%d:",__FILE__,__LINE__);x
  //#define MD13(x)
#else
  #define MD1(x)
  #define MD12(x)
  #define MD13(x)
#endif



#define D(x)
#define D1(x)
//#define MD1(x) printk("%s:%d:",__FILE__,__LINE__);x
//#define MD1(x)
#define MD2(x) printk("%s:%d:",__FILE__,__LINE__);x
//#define MD2(x)

//#define MD5(x) printk("%s:%d:",__FILE__,__LINE__);x
#define MD5(x)
//#define MD6(x) printk("%s:%d:",__FILE__,__LINE__);x
#define MD6(x)
//#define MD7(x) printk("%s:%d:",__FILE__,__LINE__);x
#define MD7(x)

//#define D0(x) printk("%s:%d:",__FILE__,__LINE__);x
#define D0(x)

//#define MD8(x) printk("%s:%d:",__FILE__,__LINE__);x
#define MD8(x)
//#define MD9(x) printk("%s:%d:",__FILE__,__LINE__);x
#define MD9(x)
//#define MD10(x) printk("%s:%d:",__FILE__,__LINE__);x
#define MD10(x)
//#define MD11(x) printk("%s:%d:",__FILE__,__LINE__);x
#define MD11(x)


#define EXT_DMA_0_START \
   do { reg_bif_dma_rw_ch3_start c = {.run=1};\
        REG_WR(bif_dma, regi_bif_dma, rw_ch3_start, (reg_bif_dma_rw_ch3_start) c); } while( 0 )
#define EXT_DMA_0_STOP \
   do { reg_bif_dma_rw_ch3_start c = {.run=0};\
        REG_WR(bif_dma, regi_bif_dma, rw_ch3_start, (reg_bif_dma_rw_ch3_start) c); } while( 0 )


#define DMA_CHUNK 0x4000 // 32-bit words - may increase??
#define CCAM_DESCR_DATA_NUM (( CCAM_DMA_SIZE  / DMA_CHUNK) +1 ) // number of data descriptors
static dma_descr_data    ccam_dma_descr_data    [CCAM_DESCR_DATA_NUM]  __attribute__ ((__aligned__(16)));
static dma_descr_context ccam_dma_descr_context __attribute__ ((__aligned__(32)));
static int dma_on=0;

int            x313_setDMABuffer(void);
unsigned long  x313_DMA_size (void);

int           x313_is_dma_on(void) {
  return dma_on;
}

int x313_dma_stop(void) {
    dma_on=0;
 MD12(printk("==========x313_dma_stop\n"));
    port_csp0_addr[X313_WA_DMACR] = 0;
    EXT_DMA_0_STOP ; 
    udelay(10) ; //?
    DMA_RESET( regi_dma9 );
  // put here restoring of the .after pointer ?
   return 0;
}


void x313_dma_start(void) {
    unsigned long dai;
    int i = 0;
 MD12(printk("----------x313_dma_start\n"));

    DMA_RESET(regi_dma9);
    for(dai = 0; dai < CCAM_DMA_SIZE; dai += DMA_CHUNK) { 
        if(dai + DMA_CHUNK >= CCAM_DMA_SIZE)  
            ccam_dma_descr_data[i].after = (char *)virt_to_phys(&ccam_dma_buf_ptr[CCAM_DMA_SIZE]);
        else  
            ccam_dma_descr_data[i].after = (char *)virt_to_phys(&ccam_dma_buf_ptr[dai + DMA_CHUNK]);
           flush_dma_descr( & ccam_dma_descr_data[i], 0);
        i++;
    }
    DMA_ENABLE(regi_dma9);
    port_csp0_addr[X313_WA_DMACR] = 0;
    DMA_WR_CMD(regi_dma9, regk_dma_set_w_size4);  

    ccam_dma_descr_context.saved_data = (dma_descr_data*)virt_to_phys(&ccam_dma_descr_data[0]);
    ccam_dma_descr_context.saved_data_buf = ccam_dma_descr_data[0].buf;
   flush_dma_descr((dma_descr_data*) & ccam_dma_descr_context, 0);
    DMA_START_CONTEXT(regi_dma9, virt_to_phys(&ccam_dma_descr_context));
    EXT_DMA_0_START ;
    port_csp0_addr[X313_WA_DMACR] = 0x30000;
    dma_on=1;
}

unsigned long x313_dma_init(void) {
    dma_on=0;
    int rslt;
    reg_dma_rw_cfg cfg = {.en = regk_dma_yes}; //  if disabled - will be busy and hang on attemt of DMA_WR_CMD
    reg_bif_dma_rw_ch3_ctrl exdma_ctrl = {
        .bw          = regk_bif_dma_bw32,
        .burst_len   = regk_bif_dma_burst8, // changed - updated FPGA to use 8-word bursts
        .cont        = 1,                   // continuous transfer mode (probably - don't care)
        .end_discard = 0,                   // discard end of burst date (don't care)
        .cnt         = 0,                   // transfer counter ignored
        .dreq_pin    = 0,                   // use hsh0
        .dreq_mode   = regk_bif_dma_norm,   // normal - active high DREQ from pin (see above)
        .tc_in_pin   = 0,                   // don't care - tc pin number
        .tc_in_mode  = 0,                   // no tc pin
        .bus_mode    = regk_bif_dma_master, // bus mode - master
        .rate_en     = 0                    // no rate limiting
    };
    reg_bif_dma_rw_ch3_addr exdma_addr = {.addr = MEM_CSR0_START | MEM_NON_CACHEABLE};
    reg_bif_dma_rw_pin0_cfg exdma_pin0 = {
        .master_ch   = 0,                   // don't care
        .master_mode = regk_bif_dma_off,    // off
        .slave_ch    = 0,                   // don't care
        .slave_mode  = regk_bif_dma_off     // off
    };
    reg_bif_dma_rw_pin1_cfg exdma_pin1 = {
        .master_ch   = 3,                   // ext DMA channel #
        .master_mode = regk_bif_dma_dack,   // use DACK, active high
        .slave_ch    = 3,                   // don't care
        .slave_mode  = regk_bif_dma_off     // off
    };
    // just in case - free DMA channel (we are only using it here)
    crisv32_free_dma(EXTDMA3_RX_DMA_NBR);
    printk("Initializing DMA registers for EXTDMA3 - ");
    MD7(printk("x313_dma_init(void)"));

    D0(printk ("before crisv32_request_dma\n");
    udelay (500000));
    rslt = crisv32_request_dma(EXTDMA3_RX_DMA_NBR,
                               "compressed data in from fpga",
                               DMA_VERBOSE_ON_ERROR,
                               0,
                               dma_ext3);
    D0(printk ("after crisv32_request_dma - result=%d\n",rslt);
    udelay(500000));

    if(rslt) {
        printk("failed\n");
        crisv32_free_dma(EXTDMA3_RX_DMA_NBR);
        printk(KERN_CRIT "Can't allocate external dma port for compressed data in from fpga");
    } else { 

        REG_WR(bif_dma, regi_bif_dma, rw_pin0_cfg, exdma_pin0); 
        REG_WR(bif_dma, regi_bif_dma, rw_pin1_cfg, exdma_pin1); 

        REG_WR(bif_dma, regi_bif_dma, rw_ch3_ctrl, exdma_ctrl);
        REG_WR(bif_dma, regi_bif_dma, rw_ch3_addr, exdma_addr);
        REG_WR(dma, regi_dma9, rw_cfg, cfg);   
    }
    x313_setDMABuffer();
    return ((unsigned long)virt_to_phys(ccam_dma_buf_ptr)) | 0x80000000;
}

int x313_setDMABuffer(void) {
    unsigned long dai;
    int i = 0;
    EXT_DMA_0_STOP; 
    for(dai = 0; dai < CCAM_DMA_SIZE; dai += DMA_CHUNK) { 
        ccam_dma_descr_data[i].buf = (char *)virt_to_phys(&ccam_dma_buf_ptr[dai]);
        ccam_dma_descr_data[i].intr = 0;
        ccam_dma_descr_data[i].wait = 0;
        ccam_dma_descr_data[i].eol = 0; 
        if(dai + DMA_CHUNK >= CCAM_DMA_SIZE) { 
        ccam_dma_descr_data[i].after = (char *)virt_to_phys(&ccam_dma_buf_ptr[CCAM_DMA_SIZE]);
            ccam_dma_descr_data[i].next = (dma_descr_data*)virt_to_phys(&ccam_dma_descr_data[0]);
        } else { 
            ccam_dma_descr_data[i].after = (char *)virt_to_phys(&ccam_dma_buf_ptr[dai + DMA_CHUNK]);
            ccam_dma_descr_data[i].next = (dma_descr_data*)virt_to_phys(&ccam_dma_descr_data[i + 1]);
        }
        flush_dma_descr( & ccam_dma_descr_data[i], 0);
        i++;
    }
    set_globalParam (G_CIRCBUFSIZE,CCAM_DMA_SIZE<<2); 
//*********************** TEMPORARY ********************************       
    MD8(printk ("filling DMA buffer with natural numbers - just test \n"));
    for(dai = 0; dai < CCAM_DMA_SIZE; dai++) ccam_dma_buf_ptr[dai] = dai;
    return 0;
}

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