|
Defines |
| #define | X313__RA__STATUS 0x10 |
| #define | X313__RA__IRQS 0x11 |
| #define | X313__RA__TRIGPH 0x12 |
| #define | X313__RA__MODEL 0x13 |
| #define | X313__RA__TABLE 0x14 |
| #define | X313__RA__SDCH0 0x20 |
| #define | X313__RA__SDCH1 0x24 |
| #define | X313__RA__SDCH2 0x28 |
| #define | X313__RA__SDCH3 0x2c |
| #define | X313__RA__SDBUF3 0x30 |
| #define | X313_SR__TRIG 20 |
| #define | X313_SR__DMA_EMPTY 19 |
| #define | X313_SR__DONE_CMPRS 18 |
| #define | X313_SR__DONE_CI 17 |
| #define | X313_SR__DCCRDY 16 |
| #define | X313_SR__DONE 15 |
| #define | X313_SR__SENST1 14 |
| #define | X313_SR__SENST0 13 |
| #define | X313_SR__NXTFR3 12 |
| #define | X313_SR__NXTFR2 11 |
| #define | X313_SR__NXTFR1 10 |
| #define | X313_SR__NXTFR0 9 |
| #define | X313_SR__PIOWEMPTY 8 |
| #define | X313_SR__PIORDY 7 |
| #define | X313_SR__CH2RDY 6 |
| #define | X313_SR__CH1RDY 5 |
| #define | X313_SR__CH0RDY 4 |
| #define | X313_SR__SCL1 3 |
| #define | X313_SR__SDA1 2 |
| #define | X313_SR__SCL0 1 |
| #define | X313_SR__SDA0 0 |
| #define | X313_SR__X323_SI 0 |
| #define | X313_SR(x) ((port_csp0_addr[X313__RA__STATUS] >> X313_SR__##x ) & 1) |
| #define | X313_PIOR(x) ((port_csp0_addr[X313__RA__IOPINS] >> X313_PIOR__##x ) & 1) |
| #define | X313_IR__VACT 0 |
| #define | X313_IR__XINT 1 |
| #define | X313_IR__XFEROVR 2 |
| #define | X313_IR__DONE 3 |
| #define | X313_IR__EOT 4 |
| #define | X313_IR__DCC 5 |
| #define | X313_IR__DONE_INPUT 6 |
| #define | X313_IR__DONE_COMPRESS 7 |
| #define | X313_IR__SMART 8 |
| #define | X313_IR(x) ((port_csp0_addr[X313__RA__IRQS] >> X313_IR__##x ) & 1) |
| #define | X313_WA_WCTL 0 |
| #define | X313_WA_DMACR 1 |
| #define | X313_WA_SENSFPN 2 |
| #define | X313_WA_VIRTTRIG 3 |
| #define | X313_WA_TRIG 4 |
| #define | X313_WA_NLINES 5 |
| #define | X313_WA_DCDC 7 |
| #define | X313_WA_COLOR_SAT 9 |
| #define | DEFAULT_COLOR_SATURATION_BLUE 0x90 |
| #define | DEFAULT_COLOR_SATURATION_RED 0xb6 |
| #define | X313_WA_FRAMESYNC_DLY 0x0a |
| #define | X313_WA_COMP_CMD 0x0c |
| #define | X313_WA_IRQM 6 |
| #define | X313_WA_COMP_TA 0x0d |
| #define | X313_WA_COMP_TD 0x0e |
| #define | X313_WA_MCUNUM 0x0f |
| #define | X3X3_AFTERWRITE {if (!port_csp0_addr[X313__RA__MODEL]) printk ("model=0");} |
| #define | x3x3_DELAY(x) {int iiii; for (iiii=0; iiii < (x); iiii++) X3X3_AFTERWRITE ; } |
| #define | X313_WA_SDCH0_CTL0 0x20 |
| #define | X313_WA_SDCH0_CTL1 0x21 |
| #define | X313_WA_SDCH0_CTL2 0x22 |
| #define | X313_WA_SD_MANCMD 0x23 |
| #define | X313_WA_SDCH1_CTL0 0x24 |
| #define | X313_WA_SDCH1_CTL1 0x25 |
| #define | X313_WA_SDCH1_CTL2 0x26 |
| #define | X313_WA_SD_MODE 0x27 |
| #define | X313_WA_SDCH2_CTL0 0x28 |
| #define | X313_WA_SDCH2_CTL1 0x29 |
| #define | X313_WA_SDCH2_CTL2 0x2a |
| #define | X313_WA_SDCH3_CTL0 0x2c |
| #define | X313_WA_SDCH3_CTL1 0x2d |
| #define | X313_WA_SDCH3_CTL2 0x2e |
| #define | X313_WA_SDPIO_NEXT 0x2f |
| #define | X313_WA_SD_PIOWIN 0x30 |
| #define | X313__X323SA__BITNM 18 |
| #define | X313__X323SA__WIDTH 1 |
| #define | X313__X323SB__BITNM 17 |
| #define | X313__X323SB__WIDTH 1 |
| #define | X313__KAI11000__BITNM 1 |
| #define | X313__KAI11000__WIDTH 1 |
| #define | X313__BAYER_PHASE__BITNM 1 |
| #define | X313__BAYER_PHASE__WIDTH 2 |
| #define | X313__AUXCLK__BITNM 3 |
| #define | X313__AUXCLK__WIDTH 1 |
| #define | X313__FILLFACTORY__BITNM 4 |
| #define | X313__FILLFACTORY__WIDTH 1 |
| #define | X313__DLYHOR__BITNM 5 |
| #define | X313__DLYHOR__WIDTH 1 |
| #define | X313__NEGRST__BITNM 6 |
| #define | X313__NEGRST__WIDTH 1 |
| #define | X313__SKIPLINEL__BITNM 7 |
| #define | X313__SKIPLINE__WIDTH 1 |
| #define | X313__XT_POL__BITNM 8 |
| #define | X313__XT_POL__WIDTH 1 |
| #define | X313__ARST__BITNM 9 |
| #define | X313__ARST__WIDTH 1 |
| #define | X313__ARO__BITNM 10 |
| #define | X313__ARO__WIDTH 1 |
| #define | X313__CNVEN__BITNM 11 |
| #define | X313__CNVEN__WIDTH 1 |
| #define | X313__EXP__BITNM 11 |
| #define | X313__EXP__WIDTH 1 |
| #define | X313__EXPPOL__BITNM 12 |
| #define | X313__EXPPOL__WIDTH 1 |
| #define | X313__TRIGSRC__BITNM 12 |
| #define | X313__TRIGSRC__WIDTH 1 |
| #define | X313__SENSTRIGEN__BITNM 12 |
| #define | X313__SENSTRIGEN__WIDTH 1 |
| #define | X313__EARLYTRIG__BITNM 14 |
| #define | X313__EARLYTRIG__WIDTH 1 |
| #define | X313__MRST__BITNM 13 |
| #define | X313__MRST__WIDTH 1 |
| #define | X313__XRST__BITNM 14 |
| #define | X313__XRST__WIDTH 1 |
| #define | X313__SCL0__BITNM 15 |
| #define | X313__SCL0__WIDTH 1 |
| #define | X313__SCL0_EN__BITNM 16 |
| #define | X313__SCL0_EN__WIDTH 1 |
| #define | X313__SDA0__BITNM 17 |
| #define | X313__SDA0__WIDTH 1 |
| #define | X313__SDA0_EN__BITNM 18 |
| #define | X313__SDA0_EN__WIDTH 1 |
| #define | X313__DCLKMODE__BITNM 19 |
| #define | X313__DCLKMODE__WIDTH 1 |
| #define | X313__PXD14__BITNM 20 |
| #define | X313__PXD14__WIDTH 1 |
| #define | X313__SCL1__BITNM 19 |
| #define | X313__SCL1__WIDTH 1 |
| #define | X313__SCL1_EN__BITNM 20 |
| #define | X313__SCL1_EN__WIDTH 1 |
| #define | X313__SDA1__BITNM 21 |
| #define | X313__SDA1__WIDTH 1 |
| #define | X313__SDA1_EN__BITNM 22 |
| #define | X313__SDA1_EN__WIDTH 1 |
| #define | X313__SOFTRST__BITNM 23 |
| #define | X313__SOFTRST__WIDTH 1 |
| #define | X313__PCLKSRC__BITNM 24 |
| #define | X313__PCLKSRC__WIDTH 2 |
| #define | X313__HFCOMP__BITNM 28 |
| #define | X313__HFCOMP__WIDTH 3 |
| #define | X313__CLKEN__BITNM 31 |
| #define | X313__CLKEN__WIDTH 1 |
| #define | X313__HACT_PHASE__BITNM 21 |
| #define | X313__HACT_PHASE__WIDTH 2 |
| #define | X313_MASK(x) (( (1 << X313__##x##__WIDTH)-1) << X313__##x##__BITNM) |
| #define | X313_BITS(x, y) (((y) & ((1 << X313__##x##__WIDTH)-1)) << X313__##x##__BITNM) |
| #define | IS_KAI11000 (ccam_cr_shadow & X313_MASK(KAI11000)) |
| #define | X313_PREPREINIT_SDCHAN(num, mode, wnr, dep, sa, ntilex, ntiley) |
| #define | X313_POSTINIT_SDCHAN(num, cmd) {port_csp0_addr[X313_WA_SDCH0_CTL0+0+((num)<<2)] = cmd } |
| #define | X313_INIT_SDCHAN(num, mode, wnr, dep, sa, ntilex, ntiley) {X313_POSTINIT_SDCHAN ( num, X313_PREINIT_SDCHAN ( num,mode,wnr,dep,sa,ntilex,ntiley ))} |
| #define | X313_CHN_EN(x) {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] |= ((4 << ((x)& 3)) | 3); } |
| #define | X313_CHN_DIS(x) {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] &= ~(4 << ((x)& 3)); } |
| #define | X313_CHN_DISALL {X3X3_AFTERWRITE ; port_csp0_addr[X313_WA_SD_MODE] &= 3 ; } |
| #define | X313_SDRAM_OFF {port_csp0_addr[X313_WA_SD_MODE]=0;} |
| #define | X313_SDRAM_ON {port_csp0_addr[X313_WA_SD_MODE]=3;} |
| #define | X313_IS_SDRAM_ON (port_csp0_addr[X313_WA_SD_MODE],((port_csp0_addr[X313_WA_SD_MODE] & 3)==3)) |
| #define | X313_CHN0_BOUND (port_csp0_addr[X313_WA_SDCH2_CTL0],(port_csp0_addr[X313_WA_SDCH2_CTL0] & 0x2000)) |
| #define | X313_XFERCNTR (port_csp0_addr[X313__RA__XFERCNTR],port_csp0_addr[X313__RA__XFERCNTR]) |
| #define | X313_HIGHFREQ (port_csp0_addr[X313__RA__HIGHFREQ],port_csp0_addr[X313__RA__HIGHFREQ]) |
| #define | X313_IRQSTATE (port_csp0_addr[0x11],port_csp0_addr[0x11]) |
| #define | X313_IOPINS (port_csp0_addr[X313__RA__IOPINS],port_csp0_addr[X313__RA__IOPINS]) |
| #define | X313_CHN0_USED |
| | X313_WA_SDCH0_CTL2 bits 12..15 are coming from dynamic register and does not depend on the written data.
|
| #define | X313_CHN0_SET_USED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0x8000; } |
| #define | X313_CHN0_SET_UNUSED { port_csp0_addr[X313_WA_SDCH0_CTL1]=0; } |
| #define | X313_SET_FPGA_TIME(x, y) { port_csp0_addr[X313_WA_RTC_USEC]= ( y ); port_csp0_addr[X313_WA_RTC_SEC]= ( x ); } |
| #define | X313_GET_FPGA_TIME(x, y) { port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]; y = port_csp0_addr[X313_WA_RTC_USEC];} |
| #define | X313_GET_FPGA_SECONDS(x) { port_csp0_addr[X313_WA_RTC_LATCH]= 0; X3X3_AFTERWRITE ; x = port_csp0_addr[X313_WA_RTC_SEC]} |
| #define | X313_MAP_FPN 0 |
| #define X313_PREPREINIT_SDCHAN |
( |
num, |
|
|
mode, |
|
|
wnr, |
|
|
dep, |
|
|
sa, |
|
|
ntilex, |
|
|
ntiley |
|
) |
|
Value:
******************************************************************************************************* ! Moved all references to FPGA access to memory-control registers here to simplify code maitenance ! when FPGA changes. ! ! Split SDARM channel initailization in 3 macros ! X313_PREINIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) - writes two (of 3) registers (not yet starting the channel) ! returns value foo the 3-rd (command) register ! X313_PREINIT_SDCHAN(num,cmd) - writes the channel command register, starting it ! waits 2 cycles after (if ETRAX FS) to make next reads safe !
X313_INIT_SDCHAN(num,mode,wnr,dep,sa,ntilex,ntiley) - combination of the 2 above, works as before ! !/ added X3X3_AFTERWRITE to be able to read FPGA after that macro (w/o -= failed in ETRAX FS)
Definition at line 1049 of file x3x3.h.
1.5.1