os/linux-2.6-tag--devboard-R2_10-4/arch/cris/arch-v32/drivers/elphel/fpgaconf333.c

Go to the documentation of this file.

/*!***************************************************************************
*! FILE NAME  : fpgaconf333.c
*! DESCRIPTION: TBD
*! Copyright (C) 2002-2004 Elphel, Inc
*! -----------------------------------------------------------------------------**
*!
*!  This program is free software: you can redistribute it and/or modify
*!  it under the terms of the GNU General Public License as published by
*!  the Free Software Foundation, either version 3 of the License, or
*!  (at your option) any later version.
*!
*!  This program is distributed in the hope that it will be useful,
*!  but WITHOUT ANY WARRANTY; without even the implied warranty of
*!  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
*!  GNU General Public License for more details.
*!
*!  You should have received a copy of the GNU General Public License
*!  along with this program.  If not, see <http://www.gnu.org/licenses/>.
*! -----------------------------------------------------------------------------**
*!  $Log: fpgaconf333.c,v $
*!  Revision 1.1.1.1  2007/08/17 10:23:18  elphel
*!  This is a fresh tree based on elphel353-2.10
*!
*!  Revision 1.7  2007/08/17 10:23:18  spectr_rain
*!  switch to GPL3 license
*!
*!  Revision 1.6  2007/07/20 10:17:45  spectr_rain
*!  *** empty log message ***
*!
*!  Revision 1.1.1.1  2007/02/23 10:11:48  elphel
*!  initial import into CVS
*!
*!  Revision 1.2  2005/05/10 21:08:49  elphel
*!  *** empty log message ***
*!
*/
/****************** INCLUDE FILES SECTION ***********************************/


#include <linux/module.h>
#include <linux/sched.h>
#include <linux/slab.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/fs.h>
#include <linux/string.h>
#include <linux/init.h>
#include <linux/autoconf.h>

#include <asm/system.h>
#include <asm/svinto.h>
#include <asm/io.h>

#include <asm/irq.h>

#include <asm/delay.h>
#include <asm/uaccess.h>
#include <asm/fpgaconfa.h>

#include "fpgaconf.h"
#include "fpgaconfi2c.h"
#include "fpgajtag.h"
#include "fpga_io.h"
#include "fpga_sdram.h"
#include "x313.h"


// TODO: Add default clock programming when powered up
// return FPGA status (and clocks) (blank, loaded + rev #), also if it is initialized (as SDRAM)
// 



#define D(x)
#define D1(x)
#define FPGA_MAJOR 129  /* LOCAL/EXPERIMENTAL */
#define MY_MODULE_DESCRIPTION "Elphel model 313 fpga/clock configuration driver"
#define FPGACONF_DRIVER_NAME "fpga/clock configuration driver v1.0n"
#define FPGACONF_MAXMINOR 10
static const char fpga_name[] = "fpga_loader";
static int minors[FPGACONF_MAXMINOR+1]; // each minor can be opened only once
static int     fpga_open   (struct inode *inode, struct file *filp);
static int     fpga_release(struct inode *inode, struct file *filp);
static int     fpga_ioctl  (struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg);
static ssize_t fpga_write  (struct file * file, const char * buf, size_t count, loff_t *off);
static loff_t  fpga_lseek  (struct file * file, loff_t offset, int orig);
static ssize_t fpga_read   (struct file * file, char * buf, size_t count, loff_t *off);

//static loff_t fpga_lseek(struct file * file, loff_t offset, int orig);
//static ssize_t fpga_read(struct file * file, char * buf, size_t count, loff_t *off);

//static int __init fpga_init(void);

static struct file_operations fpga_fops = {
        owner:    THIS_MODULE,
        open:     fpga_open,
        release:  fpga_release,
        ioctl:    fpga_ioctl,
        llseek:   fpga_lseek,
        read:     fpga_read,
        write:    fpga_write
};

//#define FPGA_STATE_LOADED       0x0000FFFF; //
//#define FPGA_STATE_CLOCKS       0x000F0000; // 
//#define FPGA_STATE_INITIALIZED  0x00100000; //
//FPGA_STATE_SDRAM_INIT 
static int fpga_state=0; 
// **************************************************************
int     initClockDefault(void) { // program clock0 to 75 MHz, clock1 - 60MHz
  int i,r;
  unsigned char d[2];
 // high byte - address, low - data
    unsigned int clocks_inits[]= \
/*      {0x1640, 0x150c, 0x1402, 0x0902, 0x0802, // clock 0 to 75 MHz
     0x42c0, 0x4109, 0x4002,
     0x45c0, 0x4409, 0x4302,
     0x48c0, 0x4709, 0x4602,
     0x4bc0, 0x4a09, 0x4902,
     0x4ec0, 0x4d09, 0x4c02,
     0x51c0, 0x5009, 0x4f02,
     0x54c0, 0x5309, 0x5202,
     0x57c0, 0x5609, 0x5502,
     0x0a02, 0x0b02    };   // clock1 to 60 MHz
*/     
        {0x1640, 0x150c, 0x1402, 0x0902, 0x0802, // clock 0 to 75 MHz   (PLL3/clkA)
     0x42c4, 0x4109, 0x4003,               // PLL1
     0x45c4, 0x4409, 0x4303,
     0x48c4, 0x4709, 0x4603,
     0x4bc4, 0x4a09, 0x4903,
     0x4ec4, 0x4d09, 0x4c03,
     0x51c4, 0x5009, 0x4f03,
     0x54c4, 0x5309, 0x5203,
     0x57c4, 0x5609, 0x5503,
     0x0a05, 0x0b05,              // clock1 to 20 MHz   (clkB)
     0x0e87    };   // PLL3->clkA, PLL1->clkB, REF->clkC, PLL2->clkD
     
        for (i=0;i<sizeof( clocks_inits)/sizeof( clocks_inits[0]);i++) {
          d[0]=((clocks_inits[i]>>8) & 0xff); // i2c address
          d[1]=( clocks_inits[i]     & 0xff); // i2c data
          if ((r=fi2c_writeData(0xd2, d, 2))) return r; // error writing to clock
        }
  fpga_state |= 0x00020000;           //#define FPGA_STATE_CLOCKS       0x000F0000; // 
  return 0;
}

/* ======================================== Top level file operations =================================================================== */
static int fpga_open(struct inode *inode, struct file *filp) {
        int p;
        int res;

        p = MINOR(inode->i_rdev);
     D1(printk("fpga_open: minor=%x\r\n",p) );
     D1(printk("filp=%lx\r\n",(unsigned long)filp) );

        switch ( p ) {
        case FPGACONF_MINOR_SDRAM : {
              if (minors[p])  return -EACCES;
// is fpga loaded?
          if ((fpga_state & FPGA_STATE_LOADED) ==     0) return -EACCES; // change to particular fpga revision
          if ((fpga_state & FPGA_STATE_CLOCKS) ==     0) return -EACCES; // clocks not running
          if ((fpga_state & FPGA_STATE_SDRAM_INIT) == 0) {
               fpga_initSDRAM();
               fpga_state |= FPGA_STATE_SDRAM_INIT;
          }
  D(printk("fsdram_open\n"));
          if ((res=fsdram_open(inode, filp))<0)return res;
          break;
        }
            case FPGACONF_MINOR_IORW :
        case FPGACONF_MINOR_I2C :
          {
           if (minors[p])  return -EACCES;
           break;
          }

        case FPGACONF_MINOR_JTAG :
          {
           if (minors[p])  return -EACCES;
// reset fpga_state
          fpga_state &= ~FPGA_STATE_LOADED;
          fpga_state &= ~FPGA_STATE_SDRAM_INIT; // not needed

// disable camera interrupts here (while reprogramming FPGA could generate interrupts;



        *R_IRQ_MASK0_CLR = 0x10;        //1 << irq_int_vector_nr
//      *R_IRQ_MASK0_CLR = IO_STATE(R_IRQ_MASK0_SET, irq_int_vector_nr, set);
        printk ("Camera interrupts disabled\n");




           if ((res =fjtag_open())) return res;
           break;      
          }

        default: return -EINVAL;
        }

        minors[p]=p;

        filp->private_data = &minors[p];

        return 0;
}
//#define FPGA_STATE_LOADED       0x0000FFFF; //
//#define FPGA_STATE_CLOCKS       0x000F0000; // 
//#define FPGA_STATE_INITIALIZED  0x00100000; // 

static int fpga_release(struct inode *inode, struct file *filp) {
   int res=0;
        int p = MINOR(inode->i_rdev);
        switch ( p ) {
        case FPGACONF_MINOR_SDRAM : {
          res= fsdram_release();
          minors[p]=0;
          return res;
        }

        case FPGACONF_MINOR_JTAG :
            if ((res=fjtag_close ()) >=0) {
               fpga_state|=1; // Add 16-bit revision number here? (from file header)
        }
// reset initializing in any case:
        fpga_state &=~FPGA_STATE_INITIALIZED;   // and fall farther...
        case FPGACONF_MINOR_I2C :
            case FPGACONF_MINOR_IORW :
          {
           minors[p]=0;
           break;
          }
        default: return -EINVAL;
        }

   D(printk("fpga_release:  done\r\n"));
        return 0;
}



static int fpga_ioctl(struct inode *inode, struct file *filp, unsigned int cmd, unsigned long arg) { // switch by minor
   int res=0;
   D(printk("fpga_ioctl cmd= %x, arg= %x\n\r",cmd,(int) arg));

          switch (((int *)filp->private_data)[0]) {

          case FPGACONF_MINOR_I2C :     // use for JTAG access ioctl also (debugging only)
           {
             switch (_IOC_NR(cmd)) {
               case I2C_WRITEREG: {
// for now - clocks are considered programmed after any successfull write to their i2c register.
// after driver will program clocks - modify that

             res=fi2c_ioctl (inode, filp, cmd, arg);
                 if (res >=0) fpga_state|=0x10000; // #define FPGA_STATE_CLOCKS       0x000F0000; // 
             return res;
           }
               case I2C_READREG: {
                   return fi2c_ioctl (inode, filp, cmd, arg);
                }
                case FPGA_PGM:
                case FPGA_STAT:
                case FPGA_JTAG:
                case FPGA_PA_RD:
                case FPGA_PA_WR:
                   return fjtag_ioctl (inode, filp, cmd, arg);
                default:return -EINVAL;
             } 
           }
      case FPGACONF_MINOR_IORW : // read write FPGA registers
           {
   D(printk("fpga_ioctl cmd= %x, arg= %x\n\r",cmd,(int) arg));

                if(_IOC_TYPE(cmd) == FPGACONF_GETSTATE) {
// just temporary...

 D(printk ("R_PORT_PA_READ=%x\r\n",(int) *R_PORT_PA_READ));

 D(printk ("R_PORT_PB_READ=%x\r\n",(int) *R_PORT_PB_READ));

                  return fpga_state;
                }
            return fpga_io_ioctl (inode, filp, cmd, arg);
           }

          default:return -EINVAL;
          }
}



static ssize_t fpga_write(struct file * file, const char * buf, size_t count, loff_t *off) {
// printk("fpga_write: ((int *)file->private_data)[0]= %x\r\n",((int *)file->private_data)[0]);
    switch (((int *)file->private_data)[0]) {
       case FPGACONF_MINOR_SDRAM :      return         fsdram_write (file, buf, count, off);
       case FPGACONF_MINOR_JTAG  :      return         fjtag_write (file, buf, count, off);
       default:                 return -EINVAL;
    }

}

static loff_t  fpga_lseek(struct file * file, loff_t offset, int orig) {
//    printk (" file=%x, offset=%x, orig=%x, ((int *)file->private_data)[0]=%x\r\n", (int) file, (int) offset, (int) orig, ((int *)file->private_data)[0]);
    D(printk (" file=%x, offset=%x, orig=%x\r\n", (int) file, (int) offset, (int) orig));
     switch (((int *)file->private_data)[0]) {
       case FPGACONF_MINOR_SDRAM :      return         fsdram_lseek(file, offset, orig);
       default:                 return -EINVAL;
    }
}

static ssize_t fpga_read(struct file * file, char * buf, size_t count, loff_t *off) {
//    return -1;
    switch (((int *)file->private_data)[0]) {
       case FPGACONF_MINOR_SDRAM :      return         fsdram_read(file, buf, count, off);
       default:                 return -EINVAL;
    }
}




//loff_t  fsdram_lseek(struct file * file, loff_t offset, int orig);
//ssize_t fsdram_read(struct file * file, char * buf, size_t count, loff_t *off);




static int __init 
fpga_init(void)
{
//  extern void init_ioremap(void);
        int i,res;
        res = register_chrdev(FPGA_MAJOR, fpga_name, &fpga_fops);
        if(res < 0) {
                printk(KERN_ERR "fpga_init: couldn't get a major number.\n");
                return res;
        }
        printk(FPGACONF_DRIVER_NAME);


        for (i=0;i<=FPGACONF_MAXMINOR;i++) minors[i]=0;
//        init_ioremap();
// Initialize ports A and B to it's default values
        initPortA();
        initPortB();

        printk("Ports A and B initialized\r\n");
        fpga_state=0;    // bit 0 - FPGA state, 1 - Clocks, 2 - SDRAM
        printk("FPGA is not loaded, clocks are not programmed, SDRAM is not initialized\r\n");
        if (initClockDefault()==0) printk("Clocks initialized (clk0=75MHz, clk1=60MHz)\r\n");
        else                       printk("Clocks initialization failed\r\n");
        return 0;
}



/* this makes sure that fpga_init is called during boot */

module_init(fpga_init);
MODULE_LICENSE("GPL");
MODULE_AUTHOR("Andrey Filippov <andrey@elphel.com>.");
MODULE_DESCRIPTION(MY_MODULE_DESCRIPTION);
MODULE_DESCRIPTION("Elphel model 333 fpga download driver");

---