67 // PL extra (non-AXI) signals 71 // Simulation signals - use same aclk 102 assign aresetn= ~
rst;
// probably not needed at all - docs say "do not use" 117 wire enough_data; // enough data to start a new burst 118 wire [11:3] next_wr_address; // bits that are incrtemented in 64-bit mode (higher are kept according to AXI 4KB inc. limit) 119 reg [31:0] write_address; 120 wire fifo_wd_rd; // read data fifo 121 wire last_confirmed_write; 124 wire [
5:
0]
arid_out;
// verify it matches wid_out when outputting data 131 reg [
7:
0]
fifo_with_requested=
0;
// fill level of data FIFO if all the requested data will arrive and nothing read 144 wire [
11:
3]
next_rd_address;
// bits that are incrtemented in 64-bit mode (higher are kept according to AXI 4KB inc. limit) 155 //awqos & {4{awvalid}} 156 assign aresetn= ~
rst;
// probably not needed at all - docs say "do not use" 157 //Supported control register fields 202 // assign rvalid= (|rcount[7:1]) || (rcount[0] && !was_data_fifo_read); 207 // AXI: Bursts should not cross 4KB boundaries (... and to limit size of the address incrementer) 208 // in 64 bit mode - low 3 bits are preserved, next 9 are incremented 215 // Current model policy is not to initiate a new burst (read from simulation port) if it may overflow FIFO 216 // - maybe the real module is done this way to aggregate external accesses. 217 // So 'assign sim_rd_ready = read_in_progress;' should be sufficient, but if that will chnage - below is 218 // full vesion that does not depend on the assumption. 225 $display (
"%m: at time %t ERROR: arsize_out=%h, currently only 'h3 (8 bytes) is valid",
$time,
arsize_out);
292 .
under (),
//waddr_under), // output reg 293 .
over (),
//waddr_over), // output reg 294 .
wcount (),
//waddr_wcount), // output[3:0] reg 295 .
rcount (),
//waddr_rcount), // output[3:0] reg 311 .
under (),
//waddr_under), 312 .
over (),
//waddr_over), 313 .
wcount (),
//waddr_wcount), 314 .
rcount (),
//waddr_rcount), 8946next_rd_addresswire[11:3]
8947read_addressreg[31:0]
8941read_in_progress_wwire
8910AFI_RDDATAFIFO_LEVELAFI_BASECTRL + 'hc
8911AFI_RDDEBUGAFI_BASECTRL + 'h10
8916VALID_ARCACHE_MASK4'b0011
8937start_read_burst_wwire
8938was_data_fifo_readreg
[31:0] 8892sim_rd_address
[DATA_WIDTH-1:0] 10452data_in
rdata_i fifo_same_clock_fill
8917VALID_ARPROT_MASK3'b010
8909AFI_RDQOSAFI_BASECTRL + 'h8
8908AFI_RDCHAN_ISSUINGCAPAFI_BASECTRL + 'h4
8907AFI_RDCHAN_CTRLAFI_BASECTRL + 'h00
8915VALID_ARLOCK_MASK2'b11
reg [DATA_DEPTH-1:0] 10459rcount
[DATA_DEPTH: 0] 10460wnum_in_fifo
reg [DATA_DEPTH-1:0] 10458wcount
8934fifo_with_requestedreg[7:0]
[DATA_WIDTH-1:0] 10453data_out
8936next_with_requestedwire[7:0]
8906AFI_BASECTRL32'hf8008000+ (HP_PORT << 12
8948last_confirmed_readwire
8940was_addr_fifo_writereg
8939was_data_fifo_writereg
[DATA_DEPTH: 0] 10461rnum_in_fifo