2672 11986WIDTH_RDP1 << (LOG2WIDTH_RD-3
12027WIDTH_RD1 << LOG2WIDTH_RD
[14-LOG2WIDTH_WR:0] 11951waddr
integer 11969LOG2WIDTH_WR5
integer 12031LOG2WIDTH_RD5
[14-LOG2WIDTH_RD:0] 11972raddr
[9 << LOG2WIDTH_RD-3-1:0] 11975data_out
11984WIDTH_WRP1 << (LOG2WIDTH_WR-3
integer 11942LOG2WIDTH_WR6
[9 << LOG2WIDTH_WR-3-1:0] 11954data_in
ram_i ramp_lt64w_64r[generate]
[9 << LOG2WIDTH_WR-3-1:0] 11980data_in
12026PWIDTH_RD(LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD
12011datap_in_extwire[WIDTH_WRP+3:0]
12009data_in_extwire[WIDTH_WR+31:0]
[9 << LOG2WIDTH_RD-3-1:0] 12019data_out
[14-LOG2WIDTH_WR:0] 12001waddr
[14-LOG2WIDTH_RD:0] 12016raddr
11981PWIDTH_WR(LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR
11985WIDTH_RD1 << LOG2WIDTH_RD
integer 11943LOG2WIDTH_RD6
12028WIDTH_RDP1 << (LOG2WIDTH_RD-3
ram_i ramp_lt64w_lt64r[generate]
12029data_out32wire[31:0]
11987data_out32wire[31:0]
ram_i ramp_64w_64r[generate]
11991datap_in_extwire[WIDTH_WRP+3:0]
[14-LOG2WIDTH_RD:0] 11946raddr
ramp_dummy_i ramp_dummy[generate]
11989data_in_extwire[WIDTH_WR+31:0]
12007WIDTH_WR1 << LOG2WIDTH_WR
ram_i ramp_64w_lt64r[generate]
[9 << LOG2WIDTH_WR-3-1:0] 12004data_in
11982PWIDTH_RD(LOG2WIDTH_RD > 2)? (9 << (LOG2WIDTH_RD - 3)): (1 << LOG2WIDTH_RD
[14-LOG2WIDTH_WR:0] 11977waddr
11983WIDTH_WR1 << LOG2WIDTH_WR
12008WIDTH_WRP1 << (LOG2WIDTH_WR-3
[9 << LOG2WIDTH_RD-3-1:0] 11949data_out
[9 << LOG2WIDTH_RD-3-1:0] 12032data_out
12005PWIDTH_WR(LOG2WIDTH_WR > 2)? (9 << (LOG2WIDTH_WR - 3)): (1 << LOG2WIDTH_WR