x393
1.0
FPGAcodeforElphelNC393camera
ram_512x64w_1kx32r.v
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1
25
/*
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Address/data widths
27
Connect unused data to 1b0, unused addresses - to 1'b1
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29
RAMB18E1 in True Dual Port (TDP) Mode - each port individually
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+-----------+---------+---------+---------+
31
|Data Width | Address | Data | Parity |
32
+-----------+---------+---------+---------+
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| 1 | A[13:0] | D[0] | --- |
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| 2 | A[13:1] | D[1:0] | --- |
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| 4 | A[13:2] | D[3:0[ | --- |
36
| 9 | A[13:3] | D[7:0] | DP[0] |
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| 18 | A[13:4] | D[15:0] | DP[1:0] |
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+-----------+---------+---------+---------+
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RAMB18E1 in Simple Dual Port (SDP) Mode
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one of the ports (r or w) - 32/36 bits, other - variable
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+------------+---------+---------+---------+
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|Data Widths | Address | Data | Parity |
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+------------+---------+---------+---------+
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| 32/ 1 | A[13:0] | D[0] | --- |
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| 32/ 2 | A[13:1] | D[1:0] | --- |
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| 32/ 4 | A[13:2] | D[3:0[ | --- |
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| 36/ 9 | A[13:3] | D[7:0] | DP[0] |
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| 36/ 18 | A[13:4] | D[15:0] | DP[1:0] |
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| 36/ 36 | A[13:5] | D[31:0] | DP[3:0] |
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+------------+---------+---------+---------+
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RAMB36E1 in True Dual Port (TDP) Mode - each port individually
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+-----------+---------+---------+---------+
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|Data Width | Address | Data | Parity |
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+-----------+---------+---------+---------+
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| 1 | A[14:0] | D[0] | --- |
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| 2 | A[14:1] | D[1:0] | --- |
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| 4 | A[14:2] | D[3:0[ | --- |
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| 9 | A[14:3] | D[7:0] | DP[0] |
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| 18 | A[14:4] | D[15:0] | DP[1:0] |
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| 36 | A[14:5] | D[31:0] | DP[3:0] |
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|1(Cascade) | A[15:0] | D[0] | --- |
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+-----------+---------+---------+---------+
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RAMB36E1 in Simple Dual Port (SDP) Mode
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one of the ports (r or w) - 64/72 bits, other - variable
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+------------+---------+---------+---------+
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|Data Widths | Address | Data | Parity |
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+------------+---------+---------+---------+
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| 64/ 1 | A[14:0] | D[0] | --- |
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| 64/ 2 | A[14:1] | D[1:0] | --- |
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| 64/ 4 | A[14:2] | D[3:0[ | --- |
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| 64/ 9 | A[14:3] | D[7:0] | DP[0] |
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| 64/ 18 | A[14:4] | D[15:0] | DP[1:0] |
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| 64/ 36 | A[14:5] | D[31:0] | DP[3:0] |
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| 64/ 72 | A[14:6] | D[63:0] | DP[7:0] |
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+------------+---------+---------+---------+
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*/
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module
ram_512x64w_1kx32r
81
#(
82
parameter
integer
REGISTERS
=
0
// 1 - registered output
83
)
84
(
85
input
rclk
,
// clock for read port
86
input
[
9
:
0
]
raddr
,
// read address
87
input
ren
,
// read port enable
88
input
regen
,
// output register enable
89
output
[
31
:
0
]
data_out
,
// data out
90
91
input
wclk
,
// clock for read port
92
input
[
8
:
0
]
waddr
,
// write address
93
input
we
,
// write port enable
94
input
[
7
:
0
]
web
,
// write byte enable
95
input
[
63
:
0
]
data_in
// data out
96
);
97
RAMB36E1
98
#(
99
.
RSTREG_PRIORITY_A
(
"RSTREG"
),
// Valid: "RSTREG" or "REGCE"
100
.
RSTREG_PRIORITY_B
(
"RSTREG"
),
// Valid: "RSTREG" or "REGCE"
101
.
DOA_REG
(
REGISTERS
),
// Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 36)
102
.
DOB_REG
(
REGISTERS
),
// Valid: 0 (no output registers) and 1 - one output register (in SDP - to lower 36)
103
.
RAM_EXTENSION_A
(
"NONE"
),
// Cascading, valid: "NONE","UPPER", LOWER"
104
.
RAM_EXTENSION_B
(
"NONE"
),
// Cascading, valid: "NONE","UPPER", LOWER"
105
.
READ_WIDTH_A
(
36
),
// Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
106
.
READ_WIDTH_B
(
0
),
// Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
107
.
WRITE_WIDTH_A
(
0
),
// Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
108
.
WRITE_WIDTH_B
(
72
),
// Valid: 0,1,2,4,9,18,36 and in SDP mode - 72 (should be 0 if port is not used)
109
.
RAM_MODE
(
"SDP"
),
// Valid "TDP" (true dual-port) and "SDP" - simple dual-port
110
.
WRITE_MODE_A
(
"WRITE_FIRST"
),
// Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
111
.
WRITE_MODE_B
(
"WRITE_FIRST"
),
// Valid: "WRITE_FIRST", "READ_FIRST", "NO_CHANGE"
112
.
RDADDR_COLLISION_HWCONFIG
(
"DELAYED_WRITE"
),
// Valid: "DELAYED_WRITE","PERFORMANCE" (no access to the same page)
113
.
SIM_COLLISION_CHECK
(
"ALL"
),
// Valid: "ALL", "GENERATE_X_ONLY", "NONE", and "WARNING_ONLY"
114
.
INIT_FILE
(
"NONE"
),
// "NONE" or filename with initialization data
115
.
SIM_DEVICE
(
"7SERIES"
),
// Simulation device family - "VIRTEX6", "VIRTEX5" and "7_SERIES" // "7SERIES"
116
117
.
EN_ECC_READ
(
"FALSE"
),
// Valid:"FALSE","TRUE" (ECC decoder circuitry)
118
.
EN_ECC_WRITE
(
"FALSE"
)
// Valid:"FALSE","TRUE" (ECC decoder circuitry)
119
// .INIT_A(36'h0), // Output latches initialization data
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// .INIT_B(36'h0), // Output latches initialization data
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// .SRVAL_A(36'h0), // Output latches initialization data (copied at when RSTRAM/RSTREG activated)
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// .SRVAL_B(36'h0) // Output latches initialization data (copied at when RSTRAM/RSTREG activated)
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/*
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parameter IS_CLKARDCLK_INVERTED = 1'b0;
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parameter IS_CLKBWRCLK_INVERTED = 1'b0;
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parameter IS_ENARDEN_INVERTED = 1'b0;
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parameter IS_ENBWREN_INVERTED = 1'b0;
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parameter IS_RSTRAMARSTRAM_INVERTED = 1'b0;
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parameter IS_RSTRAMB_INVERTED = 1'b0;
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parameter IS_RSTREGARSTREG_INVERTED = 1'b0;
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parameter IS_RSTREGB_INVERTED = 1'b0;
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*/
133
134
)
RAMB36E1_i
135
(
136
// Port A (Read port in SDP mode):
137
.
DOADO
(
data_out
[
31
:
0
]),
// Port A data/LSB data[31:0], output
138
.
DOPADOP
(),
// Port A parity/LSB parity[3:0], output
139
.
DIADI
(
data_in
[
31
:
0
]),
// Port A data/LSB data[31:0], input
140
.
DIPADIP
(
4'h0
),
// Port A parity/LSB parity[3:0], input
141
.
ADDRARDADDR
({
1'b1
,
raddr
[
9
:
0
],
5'b11111
}),
// Port A (read port in SDP) address [15:0]. used from [14] down, unused should be high, input
142
.
CLKARDCLK
(
rclk
),
// Port A (read port in SDP) clock, input
143
.
ENARDEN
(
ren
),
// Port A (read port in SDP) Enable, input
144
.
REGCEAREGCE
(
regen
),
// Port A (read port in SDP) register enable, input
145
.
RSTRAMARSTRAM
(
1'b0
),
// Port A (read port in SDP) set/reset, input
146
.
RSTREGARSTREG
(
1'b0
),
// Port A (read port in SDP) register set/reset, input
147
.
WEA
(
4'b0
),
// Port A (read port in SDP) Write Enable[3:0], input
148
// Port B
149
.
DOBDO
(),
// Port B data/MSB data[31:0], output
150
.
DOPBDOP
(),
// Port B parity/MSB parity[3:0], output
151
.
DIBDI
(
data_in
[
63
:
32
]),
// Port B data/MSB data[31:0], input
152
.
DIPBDIP
(
4'b0
),
// Port B parity/MSB parity[3:0], input
153
.
ADDRBWRADDR
({
1'b1
,
waddr
[
8
:
0
],
6'b111111
}),
// Port B (write port in SDP) address [15:0]. used from [14] down, unused should be high, input
154
.
CLKBWRCLK
(
wclk
),
// Port B (write port in SDP) clock, input
155
.
ENBWREN
(
we
),
// Port B (write port in SDP) Enable, input
156
.
REGCEB
(
1'b0
),
// Port B (write port in SDP) register enable, input
157
.
RSTRAMB
(
1'b0
),
// Port B (write port in SDP) set/reset, input
158
.
RSTREGB
(
1'b0
),
// Port B (write port in SDP) register set/reset, input
159
.
WEBWE
(
web
[
7
:
0
]),
// Port B (write port in SDP) Write Enable[7:0], input
160
// Error correction circuitry
161
.
SBITERR
(),
// Single bit error status, output
162
.
DBITERR
(),
// Double bit error status, output
163
.
ECCPARITY
(),
// Genearted error correction parity [7:0], output
164
.
RDADDRECC
(),
// ECC read address[8:0], output
165
.
INJECTSBITERR
(
1'b0
),
// inject a single-bit error, input
166
.
INJECTDBITERR
(
1'b0
),
// inject a double-bit error, input
167
// Cascade signals to create 64Kx1
168
.
CASCADEOUTA
(),
// A-port cascade, output
169
.
CASCADEOUTB
(),
// B-port cascade, output
170
.
CASCADEINA
(
1'b0
),
// A-port cascade, input
171
.
CASCADEINB
(
1'b0
)
// B-port cascade, input
172
);
173
174
endmodule
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ram_512x64w_1kx32r.11851ren
11851ren
Definition:
ram_512x64w_1kx32r.v:87
ram_512x64w_1kx32r.11858data_in
[63:0] 11858data_in
Definition:
ram_512x64w_1kx32r.v:95
ram_512x64w_1kx32r.RAMB36E1
RAMB36E1_i RAMB36E1
Definition:
ram_512x64w_1kx32r.v:97
ram_512x64w_1kx32r.11854wclk
11854wclk
Definition:
ram_512x64w_1kx32r.v:91
ram_512x64w_1kx32r.11848REGISTERS
integer 11848REGISTERS0
Definition:
ram_512x64w_1kx32r.v:82
ram_512x64w_1kx32r.11849rclk
11849rclk
Definition:
ram_512x64w_1kx32r.v:85
ram_512x64w_1kx32r.11850raddr
[ 9:0] 11850raddr
Definition:
ram_512x64w_1kx32r.v:86
ram_512x64w_1kx32r.11855waddr
[ 8:0] 11855waddr
Definition:
ram_512x64w_1kx32r.v:92
ram_512x64w_1kx32r.11853data_out
[31:0] 11853data_out
Definition:
ram_512x64w_1kx32r.v:89
ram_512x64w_1kx32r.11856we
11856we
Definition:
ram_512x64w_1kx32r.v:93
ram_512x64w_1kx32r.11857web
[ 7:0] 11857web
Definition:
ram_512x64w_1kx32r.v:94
ram_512x64w_1kx32r.11852regen
11852regen
Definition:
ram_512x64w_1kx32r.v:88
ram_512x64w_1kx32r
Definition:
ram_512x64w_1kx32r.v:80
wrap
ram_512x64w_1kx32r.v
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