x393
1.0
FPGAcodeforElphelNC393camera
oddr.v
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1
39
`timescale 1ns/1ps
40
41
module
oddr
#(
42
parameter
DDR_CLK_EDGE
=
"OPPOSITE_EDGE"
,
43
parameter
INIT
=
1'b0
,
44
parameter
SRTYPE
=
"SYNC"
45
)(
46
input
clk
,
47
input
ce
,
48
input
rst
,
49
input
set
,
50
input
[
1
:
0
]
din
,
51
output
dq
52
);
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/* Instance template for module ODDR **/
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ODDR
#(
55
.
DDR_CLK_EDGE
(
DDR_CLK_EDGE
),
56
.
INIT
(
INIT
),
57
.
SRTYPE
(
SRTYPE
)
58
)
ODDR_i
(
59
.
Q
(
dq
),
// output
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.
C
(
clk
),
// input
61
.
CE
(
ce
),
// input
62
.
D1
(
din
[
0
]),
// input
63
.
D2
(
din
[
1
]),
// input
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.
R
(
rst
),
// input
65
.
S
(
set
)
// input
66
);
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68
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endmodule
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oddr.11478rst
11478rst
Definition:
oddr.v:48
oddr
Definition:
oddr.v:41
oddr.ODDR
ODDR_i ODDR
Definition:
oddr.v:54
oddr.11480din
[1:0] 11480din
Definition:
oddr.v:50
oddr.11476clk
11476clk
Definition:
oddr.v:46
oddr.11474INIT
11474INIT1'b0
Definition:
oddr.v:43
oddr.11477ce
11477ce
Definition:
oddr.v:47
oddr.11473DDR_CLK_EDGE
11473DDR_CLK_EDGE"OPPOSITE_EDGE"
Definition:
oddr.v:42
oddr.11475SRTYPE
11475SRTYPE"SYNC"
Definition:
oddr.v:44
oddr.11481dq
11481dq
Definition:
oddr.v:51
oddr.11479set
11479set
Definition:
oddr.v:49
wrap
oddr.v
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