latch_g_ce.v

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`timescale 1ns/1ps

module  latch_g_ce#(
  parameter WIDTH = 1,
  parameter INIT = 0,
  parameter [0:0] IS_CLR_INVERTED = 0,
  parameter [0:0] IS_G_INVERTED = 0

)(
    input                rst,
    input                g,
    input                ce,
    input  [WIDTH-1: 0 ] d_in,
    output [WIDTH-1: 0 ] q_out
);
    generate
        genvar i;
        for (i = 0; i < WIDTH; i = i+ 1) begin:ldce_block
            LDCE #(
                .INIT            ((INIT >> i) & 1),
                .IS_CLR_INVERTED (IS_CLR_INVERTED),
                .IS_G_INVERTED   (IS_G_INVERTED)
            ) ldce_i (
                .Q    (q_out[i]), // output
                .CLR  (rst),      // input
                .D    (d_in[i]),  // input
                .G    (g),        // input
                .GE   (ce)        // input
            );
        end
    endgenerate


endmodule