47 input need_in,
// at least one of the channels needs access 52 wire [
width-
1:
0]
max0001,
max0203,
max0405,
max0607,
max0809,
max1011,
max1213,
max1415,
max00010203,
max04050607,
max08091011,
max12131415;
65 reg [
15:
0]
mask_prev;
// previous value of mask (invalidate if mask changes) 67 // assign mask_changed= mask!=mask_prev; 210 always @ (
posedge clk)
begin 233 //assign valid=valid_dly[3];
10604msk0809101112131415wire
10574max0001020304050607wire[width-1:0]
i_masked_max_reg masked_max_reg
10573max12131415wire[width-1:0]
10613sel00010203_rreg[1:0]
10588sel0001020304050607wire
10570max00010203wire[width-1:0]
[16*width-1:0] 10556values
10569max1415wire[width-1:0]
10603msk0001020304050607wire
10568max1213wire[width-1:0]
10565max0607wire[width-1:0]
10618sel0809101112131415_rreg[2:0]
10562max0001wire[width-1:0]
10563max0203wire[width-1:0]
10564max0405wire[width-1:0]
10572max08091011wire[width-1:0]
10616sel12131415_rreg[1:0]
10575max0809101112131415wire[width-1:0]
10614sel04050607_rreg[1:0]
10617sel0001020304050607_rreg[2:0]
10615sel08091011_rreg[1:0]
10589sel0809101112131415wire
10567max1011wire[width-1:0]
10571max04050607wire[width-1:0]
10566max0809wire[width-1:0]