x393  1.0
FPGAcodeforElphelNC393camera
sync_resets Module Reference
Inheritance diagram for sync_resets:
Collaboration diagram for sync_resets:

Static Public Member Functions

Always Constructs

ALWAYS_547  ( arst or clk [ 0 ] )
ALWAYS_548  ( clk [ 0 ] )

Public Attributes

Inputs

arst  
locked   [WIDTH - 1 : 0 ]
clk   [WIDTH - 1 : 0 ]

Outputs

rst   [WIDTH - 1 : 0 ]

Parameters

WIDTH   1
REGISTER   4

GENERATE

GENERATE [77]  

Signals

reg  en_locked
wire[WIDTH - 1 : 0 ]  rst_w
wire  rst_early_master_w
reg  rst_early_master
reg  mrst

Module Instances

level_cross_clocks::level_cross_clocks_mrst_i   Module level_cross_clocks
level_cross_clocks::level_cross_clocks_rst_i   Module level_cross_clocks [generate]

Detailed Description

Definition at line 42 of file sync_resets.v.

Member Function Documentation

ALWAYS_547 (   arst or clk [ 0 ]  
)
Always Construct

Definition at line 57 of file sync_resets.v.

ALWAYS_548 (   clk [ 0 ]  
)
Always Construct

Definition at line 65 of file sync_resets.v.

Member Data Documentation

WIDTH 1
Parameter

Definition at line 43 of file sync_resets.v.

REGISTER 4
Parameter

Definition at line 44 of file sync_resets.v.

arst
Input

Definition at line 46 of file sync_resets.v.

locked [WIDTH - 1 : 0 ]
Input

Definition at line 47 of file sync_resets.v.

clk [WIDTH - 1 : 0 ]
Input

Definition at line 48 of file sync_resets.v.

rst [WIDTH - 1 : 0 ]
Output

Definition at line 49 of file sync_resets.v.

en_locked
Signal

Definition at line 51 of file sync_resets.v.

rst_w
Signal

Definition at line 52 of file sync_resets.v.

Definition at line 53 of file sync_resets.v.

Definition at line 54 of file sync_resets.v.

mrst
Signal

Definition at line 56 of file sync_resets.v.

GENERATE [77]
GENERATE

Definition at line 77 of file sync_resets.v.

level_cross_clocks level_cross_clocks_mrst_i
Module Instance

Definition at line 68 of file sync_resets.v.

level_cross_clocks level_cross_clocks_rst_i
Module Instance

Definition at line 80 of file sync_resets.v.


The documentation for this Module was generated from the following files: