gtxe2_chnl_outclk_mux Module Reference

Inheritance diagram for gtxe2_chnl_outclk_mux:

Public Attributes

Inputs
TXPLLREFCLK_DIV1	wire
TXPLLREFCLK_DIV2	wire
TXOUTCLKPMA	wire
TXOUTCLKPCS	wire
TXOUTCLKSEL	wire [ 2 : 0 ]
TXDLYBYPASS	wire

Outputs
TXOUTCLK	wire

Defines
GTXE2_CHNL_CPLL_LOCK_TIME	60

Detailed Description

Definition at line 73 of file GTXE2_GPL.v.

Member Data Documentation

TXPLLREFCLK_DIV1 wire

Input

Definition at line 74 of file GTXE2_GPL.v.

TXPLLREFCLK_DIV2 wire

Input

Definition at line 75 of file GTXE2_GPL.v.

TXOUTCLKPMA wire

Input

Definition at line 76 of file GTXE2_GPL.v.

TXOUTCLKPCS wire

Input

Definition at line 77 of file GTXE2_GPL.v.

TXOUTCLKSEL wire [ 2 : 0 ]

Input

Definition at line 78 of file GTXE2_GPL.v.

TXDLYBYPASS wire

Input

Definition at line 79 of file GTXE2_GPL.v.

TXOUTCLK wire

Output

Definition at line 80 of file GTXE2_GPL.v.

GTXE2_CHNL_CPLL_LOCK_TIME

Define

Definition at line 91 of file GTXE2_GPL.v.

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The documentation for this Module was generated from the following files:

• x393_sata/wrapper/GTXE2_GPL.v