x393  1.0
FPGAcodeforElphelNC393camera
Static Public Member Functions | Public Attributes | List of all members
gtxe2_chnl_cpll Module Reference
Inheritance diagram for gtxe2_chnl_cpll:
Inheritance graph
[legend]

Static Public Member Functions

Always Constructs

ALWAYS_709  ( ref_clk or reset )
ALWAYS_710  ( ref_clk )

Public Attributes

Inputs

CPLLLOCKDETCLK  wire
CPLLLOCKEN  wire
CPLLPD  wire
CPLLRESET  wire
GTRSVD  wire [ 15 : 0 ]
PCSRSVDIN  wire [ 15 : 0 ]
PCSRSVDIN2  wire [ 4 : 0 ]
PMARSVDIN  wire [ 4 : 0 ]
PMARSVDIN2  wire [ 4 : 0 ]
TSTIN  wire [ 19 : 0 ]
ref_clk  wire

Outputs

CPLLFBCLKLOST  wire
CPLLLOCK  wire
CPLLREFCLKLOST  wire
TSTOUT  wire [ 9 : 0 ]
clk_out  wire
pll_locked  wire

Parameters

CPLL_CFG   [ 23 : 0 ] 29 'h00BC07DC
CPLL_FBDIV  integer 4
CPLL_FBDIV_45  integer 5
CPLL_INIT_CFG   [ 23 : 0 ] 24 'h00001E
CPLL_LOCK_CFG   [ 15 : 0 ] 16 'h01E8
CPLL_REFCLK_DIV  integer 1
RXOUT_DIV  integer 2
TXOUT_DIV  integer 2
SATA_CPLL_CFG  "VCO_3000MHZ"
PMA_RSV3   [ 1 : 0 ] 1
multiplier  CPLL_FBDIV * CPLL_FBDIV_45
divider  CPLL_REFCLK_DIV

Defines

CLOCK_DIVIDER_V  

Signals

wire  fb_clk_out
wire  reset
reg  mult_clk
reg  mult_dev_clk
time  last_edge
time  period
integer  locked_f
reg  locked
reg  tmp
reg[ 31 : 0 ]  counter

Detailed Description

Definition at line 93 of file GTXE2_GPL.v.

Member Function Documentation

ALWAYS_709 (   ref_clk or reset  
)
Always Construct

Definition at line 196 of file GTXE2_GPL.v.

ALWAYS_710 (   ref_clk  
)
Always Construct

Definition at line 199 of file GTXE2_GPL.v.

Member Data Documentation

CPLLLOCKDETCLK wire
Input

Definition at line 95 of file GTXE2_GPL.v.

CPLLLOCKEN wire
Input

Definition at line 96 of file GTXE2_GPL.v.

CPLLPD wire
Input

Definition at line 97 of file GTXE2_GPL.v.

CPLLRESET wire
Input

Definition at line 98 of file GTXE2_GPL.v.

CPLLFBCLKLOST wire
Output

Definition at line 99 of file GTXE2_GPL.v.

CPLLLOCK wire
Output

Definition at line 100 of file GTXE2_GPL.v.

CPLLREFCLKLOST wire
Output

Definition at line 101 of file GTXE2_GPL.v.

GTRSVD wire [ 15 : 0 ]
Input

Definition at line 103 of file GTXE2_GPL.v.

PCSRSVDIN wire [ 15 : 0 ]
Input

Definition at line 104 of file GTXE2_GPL.v.

PCSRSVDIN2 wire [ 4 : 0 ]
Input

Definition at line 105 of file GTXE2_GPL.v.

PMARSVDIN wire [ 4 : 0 ]
Input

Definition at line 106 of file GTXE2_GPL.v.

PMARSVDIN2 wire [ 4 : 0 ]
Input

Definition at line 107 of file GTXE2_GPL.v.

TSTIN wire [ 19 : 0 ]
Input

Definition at line 108 of file GTXE2_GPL.v.

TSTOUT wire [ 9 : 0 ]
Output

Definition at line 109 of file GTXE2_GPL.v.

ref_clk wire
Input

Definition at line 112 of file GTXE2_GPL.v.

clk_out wire
Output

Definition at line 113 of file GTXE2_GPL.v.

pll_locked wire
Output

Definition at line 114 of file GTXE2_GPL.v.

CPLL_CFG 29 'h00BC07DC
Parameter

Definition at line 117 of file GTXE2_GPL.v.

CPLL_FBDIV 4
Parameter

Definition at line 118 of file GTXE2_GPL.v.

CPLL_FBDIV_45 5
Parameter

Definition at line 119 of file GTXE2_GPL.v.

CPLL_INIT_CFG 24 'h00001E
Parameter

Definition at line 120 of file GTXE2_GPL.v.

CPLL_LOCK_CFG 16 'h01E8
Parameter

Definition at line 121 of file GTXE2_GPL.v.

CPLL_REFCLK_DIV 1
Parameter

Definition at line 122 of file GTXE2_GPL.v.

RXOUT_DIV 2
Parameter

Definition at line 123 of file GTXE2_GPL.v.

TXOUT_DIV 2
Parameter

Definition at line 124 of file GTXE2_GPL.v.

SATA_CPLL_CFG "VCO_3000MHZ"
Parameter

Definition at line 125 of file GTXE2_GPL.v.

PMA_RSV3 1
Parameter

Definition at line 126 of file GTXE2_GPL.v.

multiplier CPLL_FBDIV * CPLL_FBDIV_45
Parameter

Definition at line 128 of file GTXE2_GPL.v.

divider CPLL_REFCLK_DIV
Parameter

Definition at line 129 of file GTXE2_GPL.v.

fb_clk_out
Signal

Definition at line 134 of file GTXE2_GPL.v.

reset
Signal

Definition at line 135 of file GTXE2_GPL.v.

mult_clk
Signal

Definition at line 136 of file GTXE2_GPL.v.

mult_dev_clk
Signal

Definition at line 137 of file GTXE2_GPL.v.

last_edge
Signal

Definition at line 145 of file GTXE2_GPL.v.

period
Signal

Definition at line 146 of file GTXE2_GPL.v.

locked_f
Signal

Definition at line 147 of file GTXE2_GPL.v.

locked
Signal

Definition at line 148 of file GTXE2_GPL.v.

tmp
Signal

Definition at line 160 of file GTXE2_GPL.v.

counter
Signal

Definition at line 195 of file GTXE2_GPL.v.

CLOCK_DIVIDER_V
Define

Definition at line 220 of file GTXE2_GPL.v.

The documentation for this Module was generated from the following files: