x393  1.0
FPGAcodeforElphelNC393camera
fifo_1cycle Module Reference
Inheritance diagram for fifo_1cycle:

Static Public Member Functions

Always Constructs

ALWAYS_500  ( clk or rst )
ALWAYS_501  ( clk )

Public Attributes

Inputs

rst  
clk  
sync_rst  
we  
re  
data_in   [DATA_WIDTH - 1 : 0 ]

Outputs

data_out   [DATA_WIDTH - 1 : 0 ]
nempty   reg
half_full   reg

Parameters

DATA_WIDTH  integer 16
DATA_DEPTH  integer 4
DATA_2DEPTH  integer (1<<DATA_DEPTH)- 1

Signals

reg[DATA_DEPTH - 1 : 0 ]  fill
reg[DATA_DEPTH - 1 : 0 ]  ra
reg[DATA_DEPTH - 1 : 0 ]  wa
wire[DATA_DEPTH - 1 : 0 ]  next_fill
reg[DATA_WIDTH - 1 : 0 ]  ram [ 0 :DATA_2DEPTH ]

Detailed Description

Definition at line 44 of file fifo_1cycle.v.

Member Function Documentation

ALWAYS_500 (   clk or rst  
)
Always Construct

Definition at line 73 of file fifo_1cycle.v.

ALWAYS_501 (   clk  
)
Always Construct

Definition at line 97 of file fifo_1cycle.v.

Member Data Documentation

DATA_WIDTH 16
Parameter

Definition at line 46 of file fifo_1cycle.v.

DATA_DEPTH 4
Parameter

Definition at line 47 of file fifo_1cycle.v.

rst
Input

Definition at line 50 of file fifo_1cycle.v.

clk
Input

Definition at line 51 of file fifo_1cycle.v.

sync_rst
Input

Definition at line 52 of file fifo_1cycle.v.

we
Input

Definition at line 53 of file fifo_1cycle.v.

re
Input

Definition at line 54 of file fifo_1cycle.v.

data_in [DATA_WIDTH - 1 : 0 ]
Input

Definition at line 55 of file fifo_1cycle.v.

data_out [DATA_WIDTH - 1 : 0 ]
Output

Definition at line 56 of file fifo_1cycle.v.

nempty reg
Output

Definition at line 57 of file fifo_1cycle.v.

half_full reg
Output

Definition at line 58 of file fifo_1cycle.v.

DATA_2DEPTH (1<<DATA_DEPTH)- 1
Parameter

Definition at line 62 of file fifo_1cycle.v.

fill
Signal

Definition at line 63 of file fifo_1cycle.v.

ra
Signal

Definition at line 64 of file fifo_1cycle.v.

wa
Signal

Definition at line 65 of file fifo_1cycle.v.

next_fill
Signal

Definition at line 66 of file fifo_1cycle.v.

ram [ 0 :DATA_2DEPTH ]
Signal

Definition at line 67 of file fifo_1cycle.v.


The documentation for this Module was generated from the following files: