clock_divider Module Reference

Inheritance diagram for clock_divider:

Public Attributes

Inputs
clk_in	wire
div	wire [ 31 : 0 ]

Outputs
clk_out	reg

Parameters
divide_by	1
divide_by_param	1

Signals
reg[ 31 : 0 ]	cnt
reg[ 31 : 0 ]	div_r

Detailed Description

Definition at line 222 of file GTXE2_GPL.v.

Member Data Documentation

clk_in wire

Input

Definition at line 223 of file GTXE2_GPL.v.

clk_out reg

Output

Definition at line 224 of file GTXE2_GPL.v.

div wire [ 31 : 0 ]

Input

Definition at line 226 of file GTXE2_GPL.v.

divide_by 1

Parameter

Definition at line 228 of file GTXE2_GPL.v.

divide_by_param 1

Parameter

Definition at line 229 of file GTXE2_GPL.v.

cnt

Signal

Definition at line 231 of file GTXE2_GPL.v.

div_r

Signal

Definition at line 233 of file GTXE2_GPL.v.

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The documentation for this Module was generated from the following files:

• x393_sata/wrapper/GTXE2_GPL.v